imec’s Post

Press Release - At IEDM 2024, imec presents a new #CFET-based standard cell architecture containing two rows of CFETs with a shared signal routing wall in between. The main benefits of this double-row CFET architecture are process simplification and significant logic and SRAM cell area reduction according to imec’s design-technology co-optimization (DTCO) study. The new architecture allows standard cell heights to be reduced from 4 to 3.5T, compared to conventional single-row CFETs. ➡️ Read the full press release: https://lnkd.in/ejjV_gJa ➡️ Or learn more in our monolithic CFET paper: https://lnkd.in/eDUU4d9R ➡️ Also presented by Anne Vandooren during ITF@IEDM: https://lnkd.in/ecDXH8aM

The second RISC-V in Space Workshop (RVIS25) will take place from April 2nd to 3rd , 2025 in Gothenburg, Sweden, bringing together experts, engineers, and researchers to explore the latest innovations, applications, and challenges of RISC-V architecture in the space sector. Abstract submission is now open! 👉 https://lnkd.in/exsNQ4W5

🔥 #hottopic End-to-End Convolutional Network and Spectral-Spatial Transformer Architecture for Hyperspectral Image Classification by Shiping Li, et al. ➡️ https://brnw.ch/21wLeH8

NOW ON-DEMAND! Watch this introduction to the AMD Versal architecture, which explores the differences between the various families of AMD Versal devices, as well as delving into the different development frameworks and entry points available depending on the target application: https://lnkd.in/eZyvqJbe https://lnkd.in/ep_hHeuZ

NOW ON-DEMAND! Watch this introduction to the AMD Versal architecture, which explores the differences between the various families of AMD Versal devices, as well as delving into the different development frameworks and entry points available depending on the target application: https://lnkd.in/e-vWnXat https://lnkd.in/ebuEEGyi

Hello SmallSat - it’s been a productive week! Tomorrow, make sure to stop by my poster session on the Bosuns Locker to learn about our payload enclosure, or to just learn more about Arkisys and the Port architecture. Details below, see you at the Fieldhouse!

A paper by our team - "Constructive Plaquette Compilation for the Parity Architecture" - has been published on IOPscience! The Parity Compilation is one of the pillars of our technology, as it allows to efficiently implement the ParityQC Architecture by laying out a series of local constraints on the qubits. The ingenious layouts of the Parity Compilation allow to overcome some of the most substantial challenges on current quantum devices, where qubit numbers, connectivity and quality of operations are limited. In the newly published paper, the authors Roeland ter Hoeven, Ben Niehoff, Sagar Kale and Wolfgang Lechner present a novel constructive compilation algorithm for the ParityQC Architecture, using plaquettes for arbitrary higher-order optimization problems. The compilation process is streamlined, as the algorithm builds a rectangular layout of plaquettes, where in each layer of the rectangle at least one constraint is added. The core idea is that each constraint can be decomposed into plaquettes with a deterministic procedure, using ancillas. Read the paper here: https://lnkd.in/etp49u59

Join the online "LUMI Intro Course" that serves as an introduction to the LUMI supercomputer architecture and setup. The course will take place on 10.-11.12.2024. This course is aimed at anyone who wants to know how to perform very large computing tasks, specifically if you intend to use the LUMI supercomputer in the future. Registration is open! https://lnkd.in/e6YqYbrR #lumisupercomputer #eurohpc #hpc #uthpc #supercomputer

NOW AVAILABLE ON-DEMAND in the #element14Community! Watch this introduction to the AMD Versal architecture, which explores the differences between the various families of AMD Versal devices, as well as delving into the different development frameworks and entry points available depending on the target application: https://lnkd.in/gEXsEur6

Meta challenges transformer architecture with Megalodon LLM Megalodon also uses “chunk-wise attention,” which divides the input sequence into fixed-size blocks to reduce the complexity of the model from quadratic to linear.Read More https://ift.tt/uMIftVL https://ift.tt/KMVfw7l