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As a verification engineer, I believe that debugging issues in a code that uses bad or confusing naming convention this may rank first in the most intense pain, surpassing toothache and the pain of stubbing your little toe on a furniture! #functionalVerification

𝙑𝙀𝙍𝙄𝙁𝙄𝘾𝘼𝙏𝙄𝙊𝙉 𝘿𝙄𝘼𝙍𝙄𝙀𝙎 #6 📖 📒 📓 I asked Stefan Minić, one of our bright junior verification engineers here at Vtool - Smart Verification, who works in our office in Niš, what part of IP verification he loves the most. "𝑨𝒔 𝒔𝒐𝒎𝒆𝒐𝒏𝒆 𝒘𝒉𝒐 𝒉𝒂𝒔 𝒔𝒑𝒆𝒏𝒕 𝒒𝒖𝒊𝒕𝒆 𝒂 𝒃𝒊𝒕 𝒐𝒇 𝒕𝒊𝒎𝒆 𝒐𝒏 𝑰𝑷 𝒍𝒆𝒗𝒆𝒍 𝒗𝒆𝒓𝒊𝒇𝒊𝒄𝒂𝒕𝒊𝒐𝒏, 𝒕𝒉𝒆 𝒕𝒉𝒊𝒏𝒈 𝒕𝒉𝒂𝒕 𝑰 𝒍𝒐𝒗𝒆 𝒕𝒉𝒆 𝒎𝒐𝒔𝒕 𝒂𝒃𝒐𝒖𝒕 𝒊𝒕 𝒊𝒔 𝒕𝒉𝒆 𝒐𝒑𝒑𝒐𝒓𝒕𝒖𝒏𝒊𝒕𝒚 𝒕𝒐 𝒅𝒊𝒗𝒆 𝒅𝒆𝒆𝒑 𝒊𝒏𝒕𝒐 𝒕𝒉𝒆 𝒅𝒆𝒔𝒊𝒈𝒏'𝒔 𝒊𝒏𝒏𝒆𝒓 𝒘𝒐𝒓𝒌𝒊𝒏𝒈𝒔. 𝑻𝒉𝒊𝒔 𝒊𝒏𝒗𝒐𝒍𝒗𝒆𝒔 𝒕𝒆𝒔𝒕𝒊𝒏𝒈 𝒆𝒗𝒆𝒓𝒚 𝒔𝒊𝒏𝒈𝒍𝒆 𝒇𝒆𝒂𝒕𝒖𝒓𝒆 𝒂𝒏𝒅 𝒍𝒊𝒏𝒆 𝒐𝒇 𝒄𝒐𝒅𝒆 𝒂𝒏𝒅 𝒊𝒅𝒆𝒏𝒕𝒊𝒇𝒚𝒊𝒏𝒈 𝒂𝒏𝒅 𝒊𝒎𝒑𝒍𝒆𝒎𝒆𝒏𝒕𝒊𝒏𝒈 𝒔𝒄𝒆𝒏𝒂𝒓𝒊𝒐𝒔 𝒇𝒐𝒓 𝒆𝒗𝒆𝒓𝒚 𝒄𝒐𝒓𝒏𝒆𝒓 𝒄𝒂𝒔𝒆. 𝑨𝒏𝒅 𝒅𝒐𝒏'𝒕 𝒈𝒆𝒕 𝒎𝒆 𝒔𝒕𝒂𝒓𝒕𝒆𝒅 𝒐𝒏 𝒕𝒉𝒆 𝒔𝒂𝒕𝒊𝒔𝒇𝒂𝒄𝒕𝒊𝒐𝒏 𝒐𝒇 𝒔𝒆𝒆𝒊𝒏𝒈 𝒂 𝒅𝒆𝒔𝒊𝒈𝒏 𝒄𝒐𝒎𝒆 𝒕𝒐𝒈𝒆𝒕𝒉𝒆𝒓 𝒂𝒔 𝒊𝒕 𝒑𝒂𝒔𝒔𝒆𝒔 𝒕𝒉𝒓𝒐𝒖𝒈𝒉 𝒕𝒉𝒆 𝒗𝒆𝒓𝒊𝒇𝒊𝒄𝒂𝒕𝒊𝒐𝒏 𝒑𝒓𝒐𝒄𝒆𝒔𝒔. 𝑰𝒏 𝒇𝒂𝒄𝒕, 𝒕𝒉𝒆 𝒄𝒐𝒎𝒑𝒍𝒆𝒙𝒊𝒕𝒚 𝒐𝒇 𝒕𝒉𝒆 𝒑𝒓𝒐𝒄𝒆𝒔𝒔 𝒐𝒏𝒍𝒚 𝒂𝒅𝒅𝒔 𝒕𝒐 𝒕𝒉𝒆 𝒔𝒆𝒏𝒔𝒆 𝒐𝒇 𝒂𝒄𝒄𝒐𝒎𝒑𝒍𝒊𝒔𝒉𝒎𝒆𝒏𝒕 𝒘𝒉𝒆𝒏 𝒕𝒉𝒆 𝒋𝒐𝒃 𝒊𝒔 𝒅𝒐𝒏𝒆." Stay tuned for more stories to come. #verificationengineer #diaries #verification #bestjobever #stories ---------------------------------------- In this series, I am asking verification engineers about various aspects of their jobs. My hope is that their stories will inspire more people to truly appreciate how the job of verification engineer is interesting, challenging, and at the end of the day, very fulfilling.

Want to work as a Design & Verification Engineer ? In this video we have discussed ->The skills required to become a professional design & verification engineer. ->Vast opportunities in Design & Verification ->Who should opt for Design & Verification domain? **REGISTRATION OPEN for upcoming Design & Verification Course. (Link in comments) If you have any questions, feel free to ask them in comments.

⏳ Design Verification: The Final Countdown to Tapeout! ⏳ Ah, the life of a verification engineer… where the real fun begins when RTL passes and gate-level simulation (GLS) enters the chat. 😬 • You start with RTL, confident… until GLS hits you with timing violations and X-propagation issues. The SDF is more of a mystery novel than a file 📚. • Then comes the tapeout deadline looming on the horizon, and suddenly, every clock cycle feels like it’s on a stopwatch. 🏃♂️ • Sign-off stage? Let’s just say it’s where verification engineers test their speed and sanity—hunting down those last-minute glitches while juggling coverage reports and hoping that no sneaky bug shows up in the final netlist. 🤯 • And when that magical sign-off happens, it’s not just a project milestone. It’s a victory over timing, logic, and the universe itself! 🌟 But hey, who needs sleep when the thrill of meeting tapeout keeps you going? 😉 Kudos to everyone living this rollercoaster! Here’s to hitting those sign-off deadlines, closing the timing loops, and ensuring that the silicon dream becomes a reality. #designverification #gatelevelsimulation #tapeoutmadness #vlsi #signoffstage #verificationengineer #techhumor #weekendpost

Dive into UART Verification with UVM 🛠️ I'm thrilled to share my latest work on "UART Verification with UVM", which is designed to simplify and explain the intricate details of UART protocol verification. Whether you're just starting your journey in verification or are an experienced professional, this document will help you: 📌 Understand UART data transmission types (Simplex, Half Duplex, Full Duplex). 📌 Explore asynchronous and synchronous communication models. 📌 Grasp the intricacies of UVM-based testbenches, including transaction classes, drivers, monitors, and scoreboards. 📌 Learn through examples of randomized sequences and transaction handling for various UART configurations. 📌 Gain insights into building modular and reusable verification components. ✨ If you find this useful or have feedback, I'd love to hear your thoughts. 📬 Join my community of like-minded verification professionals, where we share knowledge, best practices, and exciting challenges in the world of chip design and verification. Let’s build and verify the future, one protocol at a time! 💡 Link to join my community : https://lnkd.in/d7skH_iA 👥 Connect with me and join the discussion in our community! #Verification #UVM #VLSI #LearningTogether #UART

𝙑𝙀𝙍𝙄𝙁𝙄𝘾𝘼𝙏𝙄𝙊𝙉 𝘿𝙄𝘼𝙍𝙄𝙀𝙎 #1 📖 📒 📓 I asked Anja Planić, one of our verification team leaders here at Vtool - Smart Verification, what part of IP verification she loves the most. "𝑻𝒉𝒆 𝒎𝒐𝒔𝒕 𝒊𝒏𝒕𝒆𝒓𝒆𝒔𝒕𝒊𝒏𝒈 𝒑𝒂𝒓𝒕 𝒇𝒐𝒓 𝒎𝒆 𝒊𝒔 𝒕𝒉𝒆 𝒄𝒓𝒆𝒂𝒕𝒊𝒗𝒊𝒕𝒚 𝒊𝒏 𝒊𝒎𝒑𝒍𝒆𝒎𝒆𝒏𝒕𝒊𝒏𝒈 𝒒𝒖𝒂𝒍𝒊𝒕𝒚 𝒄𝒐𝒅𝒆 𝒂𝒏𝒅 𝒕𝒉𝒆 𝒑𝒐𝒘𝒆𝒓 𝒐𝒇 𝒊𝒕𝒔 𝒓𝒆𝒖𝒔𝒂𝒃𝒊𝒍𝒊𝒕𝒚 𝒇𝒐𝒓 𝒕𝒉𝒆 𝒑𝒂𝒓𝒕𝒊𝒄𝒖𝒍𝒂𝒓 𝑰𝑷 𝒊𝒏 𝒕𝒉𝒆 𝒔𝒚𝒔𝒕𝒆𝒎𝒔. 𝑽𝒆𝒓𝒊𝒇𝒚𝒊𝒏𝒈 𝒂𝒏 𝑰𝑷 𝒈𝒊𝒗𝒆𝒔 𝒂𝒏 𝒆𝒏𝒈𝒊𝒏𝒆𝒆𝒓 𝒂 𝒎𝒐𝒓𝒆 𝒅𝒆𝒕𝒂𝒊𝒍𝒆𝒅 𝒆𝒙𝒑𝒍𝒐𝒓𝒂𝒕𝒊𝒐𝒏 𝒂𝒏𝒅 𝒂 𝒇𝒐𝒄𝒖𝒔 𝒐𝒏 𝒆𝒗𝒆𝒓𝒚 𝒅𝒆𝒕𝒂𝒊𝒍, 𝒘𝒉𝒊𝒄𝒉 𝒄𝒂𝒏 𝒈𝒓𝒆𝒂𝒕𝒍𝒚 𝒔𝒊𝒎𝒑𝒍𝒊𝒇𝒚 𝒕𝒉𝒆 𝒑𝒓𝒐𝒄𝒆𝒔𝒔 𝒐𝒇 𝒗𝒆𝒓𝒊𝒇𝒚𝒊𝒏𝒈 𝒄𝒐𝒎𝒑𝒍𝒆𝒙 𝒅𝒆𝒔𝒊𝒈𝒏𝒔 𝒖𝒏𝒅𝒆𝒓 𝒕𝒆𝒔𝒕." Stay tuned for more stories to come. #verificationengineer #diaries #verification #bestjobever #stories ---------------------------------------- In this series, I am asking verification engineers about various aspects of their jobs. My hope is that their stories will inspire more people to truly appreciate how the job of verification engineer is interesting, challenging, and at the end of the day, very fulfilling.

𝙑𝙀𝙍𝙄𝙁𝙄𝘾𝘼𝙏𝙄𝙊𝙉 𝘿𝙄𝘼𝙍𝙄𝙀𝙎 #2 📖 📒 📓 I asked Momcilo Kovrlija, one of our verification team leaders here at Vtool - Smart Verification and a UVM expert, what advanced UVM feature he loves the most. "𝐌𝐲 𝐟𝐢𝐫𝐬𝐭 𝐩𝐢𝐜𝐤 𝐰𝐨𝐮𝐥𝐝 𝐝𝐞𝐟𝐢𝐧𝐢𝐭𝐞𝐥𝐲 𝐛𝐞 𝐮𝐯𝐦_𝐜𝐚𝐥𝐥𝐛𝐚𝐜𝐤'𝐬. 𝐓𝐡𝐞 𝐬𝐡𝐞𝐞𝐫 𝐚𝐦𝐨𝐮𝐧𝐭 𝐨𝐟 𝐯𝐞𝐫𝐬𝐚𝐭𝐢𝐥𝐢𝐭𝐲 𝐩𝐫𝐨𝐯𝐢𝐝𝐞𝐝 𝐰𝐢𝐭𝐡 𝐭𝐡𝐞𝐢𝐫 𝐮𝐬𝐚𝐠𝐞 𝐜𝐚𝐧 𝐢𝐦𝐩𝐫𝐨𝐯𝐞 𝐭𝐡𝐞 𝐪𝐮𝐚𝐥𝐢𝐭𝐲 𝐨𝐟 𝐭𝐡𝐞 𝐞𝐧𝐯𝐢𝐫𝐨𝐧𝐦𝐞𝐧𝐭 𝐬𝐢𝐠𝐧𝐢𝐟𝐢𝐜𝐚𝐧𝐭𝐥𝐲. 𝐖𝐡𝐞𝐧 𝐢𝐦𝐩𝐥𝐞𝐦𝐞𝐧𝐭𝐞𝐝 𝐢𝐧 𝐜𝐨𝐫𝐫𝐞𝐜𝐭 𝐩𝐥𝐚𝐜𝐞𝐬, 𝐚𝐧𝐝 𝐢𝐧 𝐚 𝐜𝐨𝐫𝐫𝐞𝐜𝐭 𝐰𝐚𝐲, 𝐩𝐨𝐬𝐬𝐢𝐛𝐢𝐥𝐢𝐭𝐢𝐞𝐬 𝐠𝐚𝐢𝐧𝐞𝐝 𝐭𝐨 𝐭𝐰𝐞𝐚𝐤 𝐭𝐡𝐞 𝐞𝐧𝐯𝐢𝐫𝐨𝐧𝐦𝐞𝐧𝐭 𝐚𝐫𝐞 𝐞𝐧𝐝𝐥𝐞𝐬𝐬." Stay tuned for more stories to come. #verificationengineer #verification #uvm #stories ---------------------------------------- In this series, I am asking verification engineers about various aspects of their jobs. My hope is that their stories will inspire more people to truly appreciate how the job of verification engineer is interesting, challenging, and, at the end of the day, very fulfilling.

Looking to apply formal verification on your design? Here are some tips that can help 1. Understand Formal Verification: Recognize it as a mathematical analysis of a design's possible behaviors. Different from simulation which tests specific values, formal verification ensures comprehensive coverage. 2. Use Appropriate Tools: Tools like Jasper can visualize reaching specific states without predefined inputs. These tools compute necessary inputs, simplifying error checking and validation. 3. Leverage Advantages: Formal verification covers the entire behavior space, finding corner cases. Dynamic debugging allows live adjustments and scenario modifications. 4. Integrate into Workflow: Apply formal verification from early RTL modeling to post-silicon debugging. Utilize applications like property verification, equivalence checking, and connectivity verification. 5. Adopt a New Mindset: Shift from simulation-driven testing to formal methods. Address concerns about complexity, coverage, and training through targeted use and training. 6. Maximize Benefits: Achieve systematic, thorough validation with less effort. Increase productivity and detect bugs earlier. Use formal verification where possible, and simulate only when necessary. #FormalVerification #DesignProductivity #Validation #Simulation #RTLModeling #Debugging #Engineering #TechTips #VerificationTools #JasperTool #CircuitDesign https://lnkd.in/gVpAj8b2

5 Mistakes I made as a Verification Engineer Someone recently asked me about my experience working as a Verification engineer and if I have any advice to share to engineers starting now. I thought it would be better if I shared some of the silly mistakes I made back then. These are things I’ve learned to improve over time especially points 2 and 5 - which weren’t very clear to me at first. I still remember filing bugs without going too deep in the RTL and sometimes getting my analysis completely wrong. I also used to delete passing logs and coverage files too soon - struggling to provide results later when asked. Does this sound relatable? I’m sure you’ve made your own mistakes—comment below! 😄 #servingTheNextBug #lowpowerdesign #verification #semiconductors #verificationengineer