IC carrier board technical roadmap

Horexs professional in 0.1-0.4mm finished FR4 PCB manufacture,Used for Memory card,MEMS,CMOS,IoT,MiniLed,5G electronics and others.

Electroplating soft gold process is currently the most important surface treatment method for IC substrates, because the current W/B package is still the mainstream package; although Flip Chip has many advantages, it has no major advantages in low-end applications, and The problems of FC package equipment and yield are still under development (increasing the proportion year by year); the main disadvantage of electroplating soft gold is the cost of gold (currently Au spec Min 0.3um in the industry) and the management of the uniformity of electroplating gold/nickel; The cost management of electroplating soft gold is an important cost control content of IC substrate factories (this process accounts for more than 20% of the production cost); therefore, the technical point of electroplating soft gold is to find low-cost processes (such as ENEPIG) and uniformity improvement (improvement direction) For: graphic design and electroplating parameters, power supply form, VCP gold plating, etc.).

  At present, electroplating hard gold is also commonly used in the surface treatment of pluggable (storage) carrier boards. In addition to the cost of electroplating hard gold, the appearance of gold plating is prone to appearance due to the semi-bright or full-bright nickel plating of Watt or sulfamic acid system Poor, resulting in low yield. Yield improvement is the main technical point of hard gold plating on IC substrates; the watermark (by-product control, parameters, etc.) produced by the nickel layer is easy to react after gold plating (there is no problem with functionality, plug Only, the difference in surface cleanliness), packaging customers generally have high requirements for appearance, and the above reasons lead to the low yield of the hard gold process of the carrier (more than 85% of the finished product is already a good level);

[2] ENEPIG /Thin Ni EPIG/EPIG

  ENEPIG has seen an application boom in the past 5-10 years, mainly due to its advantages in cost and welding strength, and there is a surface treatment method called "universal" in the industry. It satisfies Wirebonding, solder ball welding, and plug connection. Reliability requirements, and with the obvious trend of high density in recent years, in order to cope with the surface treatment requirements of small spacing, at the same time, a board needs to be centralized welding method using several surface treatment methods (multiple welding function requirements). Complicated, ENEPIG is gradually being favored and applied; high-speed and high-frequency is the theme in recent years. 5G technology will be commercialized in 2020. Many products now need to ensure better line signal transmission (ENEPIG can reduce the thickness of the coating); In terms of IC substrates, due to the cost of electroplating soft gold and more and more fine-pitch products, SIP products are gradually increasing, so the demand for ENEPIG will become more obvious; at the same time, Thin Ni EPIG/EPIG technology is also the application of high-end IC substrate products in the future the trend of.

  However, the application of ENEPIG has not been as many as imagined in recent years. The main reason for restricting its promotion is the control of chemical Pd and the problem of matching with Ni tank. If the utilization rate of the entire line and the unreasonable management and design of Pd tank equipment can easily lead to its Pd Auto-deposition of the groove is accelerated. If the output of EPEIG is unstable, the running cost of the entire line will be relatively high, which is the main reason why it has been difficult to apply and promote.

Figure 17 ENEPIG's IC carrier board application field (picture from network information)

【3】OSP (Organic Soldering Protective Film)

  OSP has applications in both the PCB and IC substrate fields. At present, the application of OSP in IC substrates is relatively mature, but the main problem is that the gold surface of the mixed gold substrate has different colors; the initial water solubility and heat resistance However, OSP will cause discoloration of the gold-plated surface when it is used mixed with gold-plated substrates, so the OSP application in the industry is limited. Although some water-soluble and heat-resistant OSPs are specially developed to deal with the discoloration of the gold-plated part, they still leave the processing time too long, and the discoloration of the plated surface caused by the mixing of copper ions when processing the substrate. In the industry, Tamura WPF and SHIKOKU's OSP syrup are used in the IC substrate industry (the two are used in most IC substrate companies).

【4】Chemical silver/tin

  The application of chemical silver and chemical tin in IC substrates is not as good as that of PCBs such as automotive boards, LED\ceramic substrates, etc., and their potions are relatively mature, but the application of these two surface treatment methods in IC substrates is mainly high-end such as FCBGA product. Due to the advantages of its cost and small pitch response, there will be certain applications in the field of IC substrates in the future.

2.8 Technology Trend of Buildup & Coreless Substrate

   Laminated structure carrier board, the core layer is the same as the rigid board structure carrier board, using high Tg FR-4 or high heat resistance FR-5 or BT epoxy copper foil laminated board, in the core layer A continuous, laminated substrate for semiconductor packaging is formed by vacuum laminating resin films based on epoxy resin (such as ABF) without reinforcing materials (glass mesh). It is mainly used for the resin film of the Buildup layer, and it is the mainstream to coat the paint film on the PET film (polyethyleneterephthalate resin film). It is the same as the hard board substrate. The glass grid contains the same resin, which is raised in the vertical direction, and then formed by the method of sticking the PET film on both sides. In this chapter, the build up layer of the substrate containing the reinforcing material is used as the hard board Look at the carrier board.

  In order to form smaller holes and finer lines than the rigid board structure carrier board, the Buildup structure carrier board is mainly used for high I/O semiconductor sub-assembly MPU (Micro Processing Unit) and GPU (Graphic Processing Unit) from 750 Pin to several thousand Pin. ), ASIC (Application Specific Integrated Circuit) and other purposes. The most popular one is FC-BGA (Flip Chip-Ball Grid Array), and others also have FC-LGA (Flip Chip-Land Grid Array) or FC-PGA (Flip Chip-Pin Grid Array). Especially high-performance MPUs and ASICs used in supercomputers and high-end servers, 5+4+5 structure or 6+4+6 structure, and even 8+8+8 structure such as high multi-layer Buildup structure carrier board, Towards high-level development. In addition, in recent years, application processors and baseband processors mounted in portable digital devices such as smartphones and tablet PCs have been widely used in semiconductor packages ranging from 500Pin to 1100Pin for the purpose of miniaturization and thinning of FC-CSP (FlipChip- ChipScalePackage) carrier board. However, with regard to FC-CSP carrier boards, from the point of view of paying attention to cost, laser-drilled rigid board structure carrier boards are often used. At this time, the method used is similar to the build up process using resin film. Instead of a vacuum press, a vacuum build-up film machine that is usually used in the manufacture of copper foil laminates is used.

In addition, the PET film is coated with Buildup resin, and instead of using a continuous buildup of PP (Prepreg) and copper foil buildup. This is mainly used for the purpose of thinning, eliminating the concept of the core layer. Laminated products formed directly from only PP materials are not easy to bend. In order to obtain rigidity, PP materials with higher toughness than resin films, lower thermal expansion coefficient and high Tg are used.

【1】MircoVia/Core layer through hole connection structure

  In the Buildup structure carrier board, in order to encapsulate the high I/O narrow Pitch·Bump semiconductor chip, it is not only the fine line pattern. In order to make the PTH (Plated Through Hole) Pitch of the MicroVia and the core layer narrower, it is not enough to rely on the small diameter of mechanical drilling. By introducing the laser drilled through hole (PTV: Plated Through Via), it is in line with the conduction of each layer. Promote high-density through technology. Micro Via used to be a bottomed Via, mainly filled with electroplated filled Vias. The conduction structure is developed from a staggered structure to a stacked via structure that can be designed vertically above each layer of Via. The core layer uses mechanically drilled through holes, and the sides are copper-plated. The middle is not only filled with resin, but also the resin filled part is filled with copper. The cover plating structure is used to configure through holes vertically above the Micro Via. Moreover, in recent years, in order to thin the core layer and form a narrower through hole pitch, instead of mechanical drilling, laser processing small diameter through holes, instead of resin filling and copper plating to develop fine through hole filling technology, have begun to be used in Thin plate-centered product. The advancement of the Via conduction structure has greatly increased the design freedom of the printed circuit board. In addition, although the buildup structure (Coreless·Buildup structure) carrier board of all layers without the core layer also has the problem of warpage control during packaging, some have begun to be used in ultra-thin applications. At present, what users expect is to be able to produce Via that is almost the same as the structure of the ceramic carrier.

Figure 19 Structure diagram of various Build up products

 The FC-BGA carrier board generally adopts the product with the cover electroplating PTV+ laminated structure, and some uses adopt all-layer Buildup structure (Coreless·Buildup structure). However, semiconductor chip packaging still has problems and has not yet been popularized. On the other hand, the FC-CSP carrier board, in order to promote the thinning of the installed equipment, the thin Core+Buildup is a general structure, and the 1+2+1 structure or 2+2+2 structure has become popular, and the circuit concentration is relatively small for storage. In FC-CSP, a 3-layer Coreless·Buildup structure using PP is in use.

【2】Laminated materials

  The characteristics of the Build up layer material of the Build up structure carrier board are shown in the figure below. Among the build up layer materials, although there are products that use reinforcement materials, in order to clarify the difference with the rigid board structure carrier board, this chapter will explain the structure without reinforcement materials as the premise.

  Buildup resin is based on epoxy resin, composed of flame-retardant materials, other rubber components, and SiO2 fillers. In recent years, flame-retardant materials have changed from phosphorus series to boron series halogen-free materials, and the use of halogen-free materials in the build up structure carrier board has become standard. In addition, resin suppliers are also limited, and the standards for build up resins themselves have also improved. However, in recent years, the uses have become diverse, and the required characteristics are also varied. For example, in order to meet the requirements of high toughness, high strength, and low transmission loss at high frequencies for thin products other than fine line production; even to reduce the skin effect of high frequency signals, the performance requirements of electroless copper plating on a smooth resin surface; In response to the new requirements for high-strength resin adhesion on the smooth copper circuit surface, there are many competing resin manufacturers that are accelerating their development. It is expected that the requirements for materials that balance reliability and price will be even greater in the future, and the development of further new specifications of resin is a product of intensified competition. The main features are explained below.

-Glass transition temperature

Since the resin is cured by Oven·Cure after being laminated by a vacuum press, the glass transition temperature of the Buildup structure carrier material is different from the curing of the usual rigid board·core material vacuum laminate laminator, and is relatively low. In addition to the formal adoption of lead-free solder, as the thickness of the carrier board becomes thinner in the future, the glass transition temperature will also be required to suppress the increase in substrate warpage. At present, in terms of material cost, processability, versatility, etc., high heat-resistant epoxy resins are the mainstream. However, in order to increase Tg, the mixed use of different types of materials such as olefin series and modified novolac resins is discussed.

-Relative permittivity and dielectric loss

In order to increase the packing density of FC packages, thin and thin circuits are being sought. However, regarding the electrical properties of materials, the dielectric properties are at an important characteristic position for the integration of characteristic impedance. In addition, dielectric loss is an important cause in high-speed signal transmission. Generally, the value of reinforced material is because the glass grid reduces the dielectric loss of the dielectric, while the non-reinforced material will get lower dielectric loss. Material suppliers recommend combined materials.

-Thermal expansion coefficient

  Large-scale semiconductor chip packaging using high Tg solder and thin substrate packaging for thinner applications have both grown, so reducing the stress during packaging has become a top priority. In order to reduce the stress, it is necessary to consider including the coefficient of thermal expansion, structure and size, filler, cushioning material, and the improvement of failure stress, etc., and a comprehensive solution is the key. For the type without reinforcing material, it is necessary to reduce the coefficient of thermal expansion by modifying the mixed formula of resin, bone, and inorganic filler (SiO2). However, in order to achieve a lower coefficient of thermal expansion, the material manufacturer is even required to modify the choice of resin itself. Regarding the refinement of the circuit, the use of high-content fillers will have a direct impact on the management of the particle size of the filler itself, the thickness and width of the circuit, and the shape of the pore wall. Regarding the size of the filler particle diameter, a small one must be used, but it is restricted by cost and resin fluidity. In addition, with regard to high-content fillers, it also becomes an obstacle during laser drilling, and there are other problems with physical properties. In order to achieve a thermal expansion coefficient of 10 ppm/°C for Class A and Class B, it is necessary to develop materials that take into account production characteristics and lower prices. In order to realize the development of the thermal expansion coefficient of 10ppm/℃ level, the example of using imine resin in the insulating resin, and the bonding method of low thermal expansion coefficient materials such as liquid crystal polymer between epoxy series resin layers, etc. are combined to develop cheaper materials Still a subject.

-Peel strength

Although the peel strength of the buildup layer material is not as high as possible, it is said that it is enough to reach about 0.8kN/m in addition to the chip sensor layer on the surface. In the future, the refinement of lines will be more and more advanced, and it is difficult to ensure the bonding force due to the anchoring effect. With the increase of transmission signal speed, from the point of view of electrical characteristics, in order to control the skin effect, conductors and resin (dielectric ) The flatness of the surface. Therefore, the material manufacturer is asked not to rely on the anchoring effect and to use chemical principles to ensure the bonding force. That is, in addition to electroless copper plating on the surface of the resin, resin bonding and coexistence are sought on the surface of a smooth copper circuit.

-Young's modulus

In order to improve reliability, although it is considered to increase the Young's modulus, in contrast to the package form of the chip, the stress of the chip may be alleviated through a soft structure with a low Young's modulus. Therefore, it is important to consider the package form. On the other hand, with the progress of thinning, the warpage of the carrier becomes a problem. It is necessary to discuss the suppression of warpage by increasing the Young's modulus.

-Poisson's ratio

Due to the emergence of thin FC-CSP and Coreless carrier boards, the requirements for carrier board warpage and stress analysis during chip packaging have become stronger, but it is expected that there will be no changes in the requirements.

-Water absorption

In order to evaluate material properties, although water absorption is measured, it has passed the final carrier board reliability evaluation (reflow test, HAST (Highly-Acceleration Temperature and Humidity Test) test, and PCT (Pressure Cooker Test) test, etc.). more important. Recently, the outer layer is fabricated. At this time, due to the ion migration resistance requirement of the upper solder mask, it is also hoped that the water absorption rate will be lower.

【3】Solder Mask Material

  The solder resist material used for the surface layer particularly requires the bonding force (fluidity) with the filler during packaging and ion migration resistance. In addition, the flatness of the surface copper circuit is also required. Therefore, there have been many types of varnishes formed by screen printing or roll coating, but recently, due to improvements in portability and various characteristics, the types of films that use vacuum presses to form solder masks have increased. Although photosensitivity is the basis, with the narrower pitch and smaller size of semiconductor chip electrodes, the solder pad on the side of the carrier is required to be smaller and the pad size with good resolution. Therefore, CO2 laser, YAG laser, excimer and laser processing types have all appeared. It is basically a development that meets the cost and adapts to the requirements of their respective characteristics.

【4】Build up structure carrier board mechanical specifications

  The mechanical performance specifications of the Build up structure carrier board are shown in Table 5.3.3-1. Here, it mainly means that carrier boards that are required to be smaller and thinner for use in portable digital devices are attracting attention, and in particular, the size specifications based on thinning are estimated.

-Minimum finished product thickness

The carrier board layer is a 6-layer structure of 2+2+2, and the value is corrected. In the use of portable digital equipment, although the trend of thinning will continue in the future, the rigidity of the material will be increased, the panel (the state before the product size is divided) in the carrier board manufacturing process, etc., the transportation method and the improvement of the equipment Improvements are necessary.

-Maximum build up layers

Level A is price priority, but due to high functional requirements, in order to increase the line density, it is expected that the 3 layers will continue to be the maximum number of layers. Most products used in portable digital devices are given priority to low prices, and are expected to be designed with one or two layers. Level B is also expected to increase to 8 floors, and Level C for high-end applications with high performance is estimated to increase to 10 floors.

-Minimum Core thickness

Since there will be requirements below 30um in the future, there will be handling problems during manufacturing. In addition, the actual manufactured products must have warpage measures during and after packaging. Materials containing glass grids and their high elasticity, in addition, material suppliers need to discuss the increase in the number of laminates of the substrate within a certain thickness range (for example, 1ply→2ply), etc. The other final method for thinness is to improve production performance. In the manufacturing process of line formation, it is estimated that continuous production will be carried out through roll-to-roll equipment. In this Roadmap, the difference between the original two-layer and four-layer is abolished, especially the thinner FC-CSP and the size of the carrier board. In order to suppress the warpage of the substrate, a certain degree of thickness must be differentiated from the FC-CSP , Modify the content in the table.

-Minimum Buildup layer thickness

The thinning of the buildup layer not only needs to consider issues such as portability and electrical insulation, but also electrical considerations such as controlling characteristic impedance for making signal lines. That is, the thickness and variation of the buildup layer as the insulating layer, the line width and its variation, etc., must be fully considered in terms of design and manufacturing. At this stage, the interlayer insulation is 25um as the limit. As the wire layer becomes thinner, it will become thinner.

-Warpage specifications

Due to the miniaturization of the chip connection Pad Pitch, the increase in the number of Pads and the smaller Bump diameter, the warpage requirements are more stringent. On the other hand, due to the thinning of the carrier board, it is easy to warp. Therefore, warping must be considered from all angles from the design stage to the structure of the carrier board, material properties, manufacturing process, and thermal history of the package. In particular, for the recent narrow-pitch bonding products, the usual automatic alignment is used instead of the solder-solder combination, and the absolute amount of solder paste is reduced. The high-precision Chip Bonder is used to place the solder on the chip and carrier side in advance. Full alignment, thermal compression bonding under low load (ThermalCompression Bonding) was also discussed. In this case, the excessive flatness of the solder joint surface requires the coplanar flatness to be 10um or less.

[5] Conductor size specifications of Buildup structure carrier board

The conductor size specifications of the Buildup structure carrier board are shown in the figure below.

-Minimum copper foil thickness

The requirement for thinning of copper foil is mainly for the production of fine circuits, but the reduction in peel strength and the increase in cost must be considered. The actual power/ground plane layer in the inner layer of the core layer cannot be reduced in size, so the thickness of the copper foil cannot be reduced. However, it is estimated that a thin copper foil thickness is required from the viewpoint of ensuring the flatness of the Buildup insulating layer near the surface of the core layer of the Buildup layer.

-Minimum conductor thickness

The thickness of the conductor on the buildup layer refers to the case of electrolytic copper plating on the base copper and the case of electroless copper plating. Electroless copper plating can make the thickness of the conductor thinner. In addition, in order to make fine lines, the line width and thickness must be thin, and the reliability of the thickness must be considered. In recent years, the use of copper plating to fill holes has been improved. In this way, the aspect ratio of the hole largely depends on the hole filling performance, and the thickness of the line width has to be determined by considering the hole filling performance.

-Minimum line width, line width tolerance, minimum line distance

  There has been progress in line width refinement. It has been improved by using dry film, exposure machines (using direct imaging exposure, projection exposure, etc.), and electroplating solutions. It is expected that it is still possible to extend the existing manufacturing process to 10um, and even the requirements below 10um Can correspond. However, new materials and some new equipment must be introduced, and the rising manufacturing cost has become a state of no choice. The development capabilities expected of equipment manufacturers in the future include materials, auxiliary materials and potions.

  In the short term, requirements below 5um will be put forward. The flatness and smoothness of the bottom copper insulating material have become an important reason. In particular, the bottom copper material has the following two problems. 1 When removing the glue residue at the bottom of the hole, only select the hole part, and the surrounding resin surface is not rough enough and must be cleaned. 2 At present, the anchor effect is mainly used to maintain the strength of copper plating. In order to respond to refinement and electrical characteristics, how to ensure the strength of the plating surface on a smooth surface becomes a problem. In addition, due to the extremely low coefficient of thermal expansion, the amount of inorganic fillers contained increases, and its size is also developing towards miniaturization, and the influence on the fluidity of the resin cannot be ignored. In order to ensure the flatness of the resin surface, the allowable range of resolution during fine circuit exposure is narrowed, and its influence must also be considered.

[6] Hole specification of Buildup structure carrier board

The hole size specifications of the Buildup structure carrier board are shown in the figure below.

-Minimum core hole diameter

The mainstream processing method used for the through holes in the core layer is mainly mechanical drilling. However, for recent thin substrates, laser drilling that can process small apertures is selected. Through holes, copper foil and insulating layer must be processed at the same time (generally, reinforcing materials such as glass mesh are added). However, such materials have different wavelengths of laser light absorption. The glass mesh is specially coated to improve the absorption of the laser, and the surface treatment of the copper foil is used, and efforts must be made in the laser irradiation method. On the other hand, although mechanical drilling has excellent production performance in the state where multiple pieces of core material are stacked, the strength and wear of the drill when the hole diameter is small, the machining accuracy is low due to the vibration of the drill shaft, The diameter is also limited. At present, through high-precision drilling and optimization of the number of laminated plates during processing, recently small apertures below 100um diameter can also be processed for mass production. However, when the diameter of the through hole of a particularly thin product is below 100um, CO2 laser processing is more common than mechanical drilling.

-Minimum Land size of core through hole

At present, the width of the ring of grade A is 20um (laser drilling) or 25um (mechanical drilling), and there is a tendency to decrease. But even if each grade is reduced by about 5um, the smaller land size depends on the smaller pore size. Therefore, to improve the accuracy of land size and land position, it is not only the hole diameter, but the combination of the expansion and contraction of the substrate and the drilling machine is more important.

-Minimum pitch of core through hole

The core hole pitch is affected by the accuracy of Land position and the distance between adjacent hole walls. In particular, how high the accuracy of the Land position can be improved is very important. In addition, to ensure insulation, a certain distance between the hole walls must be ensured. In particular, it refers to the use of laser drilling to make through holes and pattern processing during exposure in thin substrates with large fluctuations in expansion and contraction. Generally, the substrate does not use the global alignment method of four-corner alignment, but also uses some parts. Counterpoint. In the production of ultra-fine circuits, segmented exposure is used, and the partial or area registration method that is linked to the segmented exposure machine and the production performance is somewhat reduced is introduced.

-Minimum aperture of Micro Via blind hole

The Micro Via production technology of the mainstream Buildup layer is processed by CO2 laser. The target of laser processing is to add reinforcement materials and buildup layer materials without reinforcement materials, no matter what thermosetting epoxy resin is the mainstream. The requirements for aperture and position accuracy are increasing every day. Recently, the development of high-precision large-diameter global mirror (GlobalMirror) is being promoted. Processing time is not reduced, and small diameter holes can be processed with high precision. When processing Vias below 30um, non-CO2 lasers, but also UV-YAG lasers with slower processing speeds are used. In the future, the size will be smaller. Regarding the processing of Buildup resin with glass mesh, the most suitable specifications must be determined according to their respective costs.

-Micro Via minimum Land size

The ring width of grade A is almost close to the position accuracy of the surface solder mask. It is expected that in the future, grade A and grade B will shrink by about 5um, while grade C will shrink by about 15um. The expansion and contraction of the substrate and the accuracy of the laser drilling machine itself are expected to be realized through future development.

-Micro Via minimum pitch

As the pad pitch of the semiconductor chip connection shrinks, the minimum pitch of the non-through hole Micro Via must also be reduced. Therefore, in order to make Micro Via, there must be a technology to identify the connection Land under the insulating layer and control the processing position. In the future, the pitch required for laser drilling will reach 50um.

-Minimum copper plating thickness for core via via

When fine lines are required on the surface of the core layer, in general, the plating thickness of the through hole must be thinner, and the hole wall crack and the disconnection of the shoulder of the through hole must be fully confirmed. Therefore, when making fine lines on the surface of the core layer, on the basis of ensuring the minimum copper plating thickness of the core layer vias, it must be a process that can produce a thin core layer copper plating thickness (thin copper foil, etching, mechanical grinding, etc.) , There must be a countermeasure for CAF between through holes. In addition, the thinning of the core layer and the popularization of products using hole-filled plating.

-Minimum copper plating thickness in the buildup layer hole

The copper plating thickness in the buildup layer hole is expected to be thinner as the thickness of the insulating layer becomes thinner and the hole diameter becomes smaller. However, with the advancement of high density, due to the formation of stacked holes, the use of copper-plated hole filling is generally increased in the carrier board design. Therefore, based on the broad direction of the Roadmap correction, it is estimated that the copper-plated hole filling will become a standard structure. In hole filling, in order to make fine lines, the flatness of the Build layer on MicroVia is required.

-Permissible tolerance of characteristic impedance of Buildup structure carrier board

The allowable tolerance of characteristic impedance of the buildup structure carrier board is shown in Table 5.3.7-1. The characteristic impedance has a great influence on the line width and the thickness of the insulating layer, and it becomes very important to improve the engineering capability in terms of size. At the same time, by correctly grasping the relationship between the design value and the measured value, the composite factors such as the stable material property value are relatively large.

The yellow mark means that a solution can be found on the current extension line.

[7] Dimensions of all layers of Buildup structure (Coreless·Build up structure)

In the cross-sectional structure, the substrate made of PP material with stacked holes structure in all layers is called Coreless. Especially FC-CSP for storage and low-cost application processors has begun to be adopted. However, because the glass grid and process are similar to the rigid board structure carrier board, in this chapter, there is no corresponding situation as the Buildup structure carrier board. The three-layer glass grid reinforced coreless structure is used as the PoP DRAM packages have begun mass production.

The build up structure of all layers here basically assumes that the resin layer and copper-plated circuit are repeated on the Core layer, and the common Build up structure carrier board does not have a core layer.

Although carrier boards with build-up structures of all layers are commonly used in high-performance semiconductors such as MPUs of major snap-on game consoles, chip packaging is not easy and the expected cost advantage has not been achieved, so it has not yet been popularized. On the other hand, the existing core layer is thinner to improve the electrical characteristics, the stress is relieved to improve the reliability of Via·Hole, and the application of thinning is promoted. Regarding large-scale semiconductor chips (processors), due to good packaging, it is expected that the most powerful candidate for all laminated hole structures is to adopt the direction of thin core boards. Coreless structure is estimated to be not widely used.