Implementation Challenges of Chip

The metric for today's ASIC is the maximum number of devices integrated, reduced die-size,optimal power,speed,thermal performance, addressing signal integrity, addressing reliability, enhanced yield techniques, reducing PLL jitters for reliable functionality, testability,integration of analog and digital in single SoC, Lithography friendly DRC, Functionality met, high speed interfaces to memories, the IO fabric, IO buffer analysis and selection, implementation to validate the silicon, ability to in-corporate last minute spec changes/functional & timing bugs Engineering Change Orders, Optimized package feasible, development phases involving multi-geographical multi-site, complex database handling, various models/abstractions/standards/formats/Protocols, advanced process, library characterization modelling silicon, higher degree of EDA tools, design re-use standards, building designs robust enough to deal with EMI noise/package noise/power-ground noise/cross-talk noise/substrate-noise/clock-jitter/process uncertainties/IR-drop/On-chip variation and on other side of the coin, how to address all these issues right from the design stage is the challenge of today's Chip Design Industry.

This tight bonding of integration across the domains/abstractions/tools/designers/process/protocols/standards/design re-use/decision in optimal trade-offs/design know-how's/cross-culture design community needs a modular uniform approach , to bring first pass silicon success. Now let's deal with the Implementation challenges and steps to achieve it in the design-phase.

Complex Database Handling/Multi-site Design & Development As now the designs are development in multi-site environment, as each site has some domain expertise and to use to the fullest it needs multi-site design and development stages, in order to maintain the database handling a proper version control management System (e.g., clearcase) is required to proper align the database , tag it with labels to know the database and finally after designing go through with proper reviews and checklist process to assure the quality of the delivery.Designing an Optimal Padring Steps involved in designingan optimal padring

Make sure you have corner-pads, across all the corners of the padring This is mainly to have the power-continuity as well as the resistance is less Ensure that the Padring fulfills the ESD requirement,

Identify the power-domains,split the domains, Ensure common ground across all the domains. Ensure thatthe design has sufficient core power-pads.

Choose the Drive-strength of the pads based on the current requirements, timing.

 Ensure that there is separate analog ground and power pads. A No-Connection Pad is used to fill out the pad-frame if there is no requirement for I/O's.

Extra VDD/GND pads also could be used. Ensure that no Input/output pads are used with unconnected inputs, they consume power if the inputs float.

 Ensure that oscillator-pads are used for clock inputs. In-case if the design requirement for source synchronous circuits make sure that the clock and data pads are of same drive-strength.

Breaker-pads are used to break the power-ring, and to isolate the power-structure.

 Ensure that the metal-wire connected to the pin can carry sufficient amount of the current, check if more than one metal-layer is necessary to carry the maximum current provided at the pin.

Ensure that few pad-filler cells are placed near the corner pads to ease the substrate routing requirements. In case of source synchronous pads, like clock and data going out, Ensure that these pads are on the centre, as the leads at the center of the package is short compared to the leads on the corners of the package, which can reduce the impact of EMI.

Designing for Optimized Area As silicon real-estate is very costly and saving is directly proportional to the company's revenue generation lot of emphasize is to design which has optimal utilization in the area-front.

If the path is not timing-critical, then optimize the cells to use the low-drive strength cells so that there will saving in the area. Abut the VDD rows Analyzing the utilization numbers with multiple floor-planning versions which brings up with optimized area targets.

Designing an Optimized floorplan Study the data-flow graph of the design and place the blocks accordingly, to reducing the weighted sum of area, wire-length.

Minimize the usage of blocks other-than square shapes, having notches Place the blocks based on accessibility/connectivity, thereby reducing wire-length. About the memory, if the pins are one-sided, there-by area could be reduced. If the memory communicates to the outside world more frequently, then placing at the boundary makes much of a sense. Study the number of pins to be routed, with the minimum metal width allowed, estimate the routability issues. Study the architecture and application , so that the blocks which will be enabled should be scattered, to reduce the power-ground noise.

Designing for Achieving Power-targets As Today's IC design power plays a major-role in the design win, achieving power-targets are the major concern. Some of the design best-practices are Design with Multi-VDD designs, Areas which requires high performance, goes with high VDD and areas which needs low-performance are working with low Vdd's, by creating Voltage-islands and making sure that appropriate level-shifters are placed in the cross-voltage domains Designing with Multi-Vt's(threshold voltages), areas which require high performance, goes with low Vt, but takes lot of leakage current, and areas which require low performance with high Vt cells, which has low leakage numbers, by incorporating this design process, we can reduce the leakage power. As in the design, clocks consume more amount of power, placing optimal clock-gating cells, in the design and controlling them by the module enables gives a lot of power-savings. As clock-tree's always switch making sure that most number of clock-buffers are after the clock-gating cells, this reduces the switching there by power-reduction. Incorporating Dynamic Voltage & Frequency scaling (DVFS) concepts based on the application , there by reducing the systems voltage and frequency numbers when the application does not require to meet the performance targets. Ensure the design with IR-Drop analysis and ground-bounce analysis, is with-in the design specification requirement. Place power-switches, so that the leakage power can be reduced.

Designing for Achieving Frequency targets. As ASIC designs are today rated by the clock frequency the design can achieve, brings with lot of performance within. The few design strategies to achieve the frequency targets.

Using logic restructuring for the areas to be timing met,Use the useful skew , if permissible by meeting the hold-time requirements. Use register retiming/time-borrowing concepts to meet the design timing requirements Use faster flip-flops for the timing-paths which are timing hungry. Use Low-Vt cells for the paths to meet the timing. Ensuring the design meets the frequency targets by performing STA, across all the functional and test modes , across all the corners, including the derating factors. Make sure that there exists common clock-tree paths and bifurcation happens only at the last-stage, so that the common clock-path can be removed in the delay calculation as over-head in the pessimism removal during de-rating. Incorporate programmable DLL(Delay locked loop) based design, for memory-controller designs, which involves round-trip delays.

Designing for Meeting Signal-integrity targets As more and more devices are getting packed, results in more congested areas, and coupling capactiances dominating the wire-capacitance, creates SI violations.Let's see now by what are all the measures we can reduce/solve it.As clock-tree runs across the whole chip, optimizing the design for SI, is essential route the clock with double-pitch and triple spacing. In-case of SI violation, spacing the signal nets reduces cross-talk impacts. Shield the nets with power-nets for high frequency signal nets to prevent from SI. Enable SI aware routing , so that the tool takes care for SI

Ensure SI enabled STA runs, and guarantee the design meeting the SI requirements Route signals on different layers orthogonal to each other.Minimize the parallel run-length wires, by inserting buffers.Designing for Better Yield(DFY/DFM) Better yield could be achieved by reducing the possibility of manufacturability flaws. Guaranteeing the circuit performance byducing parametric yield, with process variations playing a major role is a big-challenge.

Create more powerful stringent runset files with pessimistic spacing/short rules. Check for the areas where the design is prone to lithographic issues, like sharp cuts and try to re-route it. Forvia-reliability issues, use redundant vias, to reduce the chances for via-breakage. In order to design for yield-enhancement , design systems, which could have optimal redundancy, like repairable memories. Optimal placing of decoupling capacitances, reduces the power-surges. Doubling the width of the non-critical nets, clock-nets can increase the yield parameter. Ensure that the poly-orientation are maintained.

Designing for Optimal integration of Analog and Digital As today's IC has analog components also inbuilt , some design practices are required for optimal integration. Ensure in the floorplanning stage that the analog block and the digital block are not siting close-by, to reduce the noise. Ensure that there exists separate ground for digital and analog ground to reduce the noise. Place appropriate guard-rings around the analog-macro's. Incorporating in-built DAC-ADC converters, allows us to test the analog portion using digital testers in an analog loop-back fashion. Perform techniques like clock-dithering for the digital portion.Designing for Engineering Change Order As more and more complex the IC design is , and with lot of first time application , is more prone to last minute changes, there should be provision in the design-flow to accommodate the functional and timing bugs. The step to perform this called as Engineering change order(ECO).Ensure that the design has spare functional gates well distributed across the layout. Ensure that the selection the spare gates, has many flavours of gates and universal gates, so that any functionality could be achieved.Designing an Lithography friendly Design Designing for Manufacturability requires validating the design full-filling lithography rules.Checking the layout confirming the design rules (spacing,trace-width,shorts). Check for the less-congested areas and increasing the spacing of the nets

The writer is a techsavy and working in a semiconductor company