[en] A control and data acquisition system has been designed for the CDF Silicon Vertex Detector (SVX) at Fermilab. The system controls the operation of the SVX Rev D integrated circuit (SVX IC) that is used to instrument a 46,000 microstrip silicon detector. The system consists of a Fastbus Sequencer, a Crate Controller and Digitizer modules. 11 refs., 6 figs., 3 tabs

[en] In July, 1975 efforts were initiated to develop a new standard structure for processing digital information with emphasis on very large, very high data rate experiments. This effort is currently called the ''FASTBUS''. At this time, the design of the bus appears to be solidifying--at least to the extent that the specifications can be ''tried on for size'' to a real project. At Fermilab a commitment has been made to use the FASTBUS in the Colliding Detector Facility and a smaller preliminary project, E594. This study examines these projects for fit

[en] A new crate-based front end system has been built which features low cost, compact packaging, command capability, 16 bit dynamic range digitization, and a high degree of redundancy. The crate can contain a variety of instrumentation modules, and is designed to be situated close to the detector. The system is suitable for readout of a large number of channels via parallel multiprocessor data acquisition

[en] A digital processor is described which reconstructs mass and momentum as a second-level trigger selection. The processor is a five-address, microprogramed, pipelined, ECL machine with simultaneous memory access to four operands which load two parallel multipliers and an ALU. Source data modules are extensions of the processor

[en] The M7 is a small fast computer with an instruction set designed to match the on-line pattern recognition problems of a high energy physics experiment. It has been used as a trigger processor in a photoproduction experiment at Fermilab. The full off-line track-finding program is being moved to the M7 to allow on-line selection of events based on detailed information and to relieve the burden on the central laboratory computer facility. The hardware, support software, and applications programs are discussed

[en] A new crate-based front end system has been built which features low cost, compact packaging, command capability, 16 bit dynamic range digitization, and a high degree of redundancy. The crate can contain a variety of instrumentation modules, and is designed to be situated close to the detector. The system is suitable for readout of a large number of channels via parallel multiprocessor data acquisition. The Rabbit system is being used at the CDF

[en] A new crate-based front end system has been built featuring low cost, compact packaging, fast readout, command capability, 16 bit digitiziation, and a high degree of redundancy. The crate can contain a variety of instrumentation modules and is designed to be placed near the detector. Remote, special purpose processors direct the data readout. Channel-by-channel pedestal subtraction and threshold comparison in the crate allow the skipping of empty channels. The system is suitable for the readout of a very large number of channels. (orig.)

[en] The SVX data acquisition system includes three components: a Fastbus Sequencer, an SVX Rabbit Crate Controller and a Digitizer. These modules are integrated into the CDF DAQ system and operate the readout chips. The results of the extensive functional tests of the SVX modules are reported. We discuss the stability of the Sequencers, systematic differences between them and methods of synchronization with the Tevatron beam crossings. The Digitizer ADC calibration procedure run on the microsequencer is described. The microsequencer code used for data taking and SVX chip calibration modes is described. Measurements of the SVX data scan time are discussed

[en] As part of the upgrade program at CDF, electronics has been built to bring the shower max (CES) and preshower (CPR) data into the trigger at level 2. After each crossing, 384 bits from shower max and 192 from the preshower wires are latched. Data from tracks are bussed to this module to provide the wire address and momentum which are then successively compared to the wire data in large look-up tables. Approximately 50 nanoseconds is required to determine a match, write the results in FIFO, and make the results available to track memory. Monte Carlo analysis has indicated that an increase in efficiency of a factor of three in triggering on b decays will be achieved with this hardware

[en] As part of the upgrade program at CDF, electronics has been built to bring the shower max (CES) and preshower (CPR) data into the trigger at level 2. After each crossing, 384 bits from shower max and 192 from the preshower wires are latched. Data from tracks are bussed to this module to provide the wire address and momentum which are then successively compared to the wire data in large look-up tables. Approximately 50 nanoseconds is required to determine a match, write the results in FIFO, and make the results available to track memory. Monte Carlo analysis has indicated that an increase in efficiency of a factor of three in triggering on b decays will be achieved with this hardware