Josep Rius - researchr alias

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Viewing Publication 1 - 20 from 20

2021

CatDetect, a framework for detecting Catalan tweetsSergi Plaza, Jordi Vilaplana, Jordi Mateo, Josep Rius, Francesc Solsona. mta, 80(7):10657-10677, 2021. [doi]

2015

Supply Noise and Impedance of On-Chip Power Distribution Networks in ICs With Nonuniform Power Consumption and Interblock Decoupling CapacitorsJosep Rius. tvlsi, 23(6):993-1004, 2015. [doi]

2013

IR-Drop in On-Chip Power Distribution Networks of ICs With Nonuniform Power ConsumptionJosep Rius. tvlsi, 21(3):512-522, 2013. [doi]

2010

A method for detecting resistive opens in busesJosep Rius. iolts 2010: 187-189 [doi]

A single conductive surface as communication media for networked devicesJosep Rius. bodynets 2010: 52-58 [doi]

Two-dimensional communication of networked devices through a single conductive surfaceJosep Rius. inss 2010: 115-122 [doi]

2009

Analysis of the extra delay on interconnects caused by resistive opens and shortsPablo Maqueda, Josep Rius. iolts 2009: 208-209 [doi]

A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital CircuitsJosep Rius, Luis Elvira Villagra, Maurice Meijer. ets 2009: 135-140 [doi]

Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling CapacitorsJosep Rius, Maurice Meijer. jssc, 44(2):484-494, 2009. [doi]

2006

An Activity Monitor for Power/Performance Tuning of CMOS Digital CircuitsJosep Rius, Maurice Meijer, José Pineda de Gyvez. jolpe, 2(1):80-86, 2006. [doi]

2005

An Activity Monitor for Power/Performance Tuning of CMOS Digital CircuitsJosep Rius, José Pineda de Gyvez, Maurice Meijer. patmos 2005: 187-196 [doi]

2004

BIST Technique by Equally Spaced Test Vector SequencesSalvador Manich, L. García, L. Balado, E. Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras. vts 2004: 206-216 [doi]

2003

On the selection of efficient arithmetic additive test pattern generators [logic test]Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, R. Rodriguez, Joan Figueras. ets 2003: 9-14 [doi]

Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental ResultsJosep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodriguez-Sánchez. patmos 2003: 80-89 [doi]

2002

Comparison of IDDQ Testing and Very-Low Voltage TestingBram Kruseman, Stefan van den Oetelaar, Josep Rius. itc 2002: 964-973 [doi]

1999

Exploring the Combination of IDDQ and iDDt Testing: Energy TestingJosep Rius, Joan Figueras. date 1999: 543-548 [doi]

1998

IDDQ testing: state of the art and future trendsAntoni Ferré, Eugeni Isern, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras. integration, 26(1-2):167-196, 1998. [doi]

1996

Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experimentsJosep Rius, Joan Figueras. et, 9(3):295-310, 1996. [doi]

1995

Detecting I/sub DDQ/ defective CMOS circuits by depoweringJosep Rius, Joan Figueras. vts 1995: 324-329 [doi]

1992

Proportional BIC sensor for current testingJosep Rius, Joan Figueras. et, 3(4):387-396, 1992. [doi]

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