Table of Contents

• A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement techniqueGeorgios Karakonstantis, Charles Augustine, Kaushik Roy. 3-8 [doi]
• Predictive error detection by on-line aging monitoringJulio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira. 9-14 [doi]
• Temperature dependence of NBTI induced delaySeyab Khan, Said Hamdioui. 15-20 [doi]
• Aging test strategy and adaptive test scheduling for SoC failure predictionHyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara. 21-26 [doi]
• Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layoutsPaolo Rech, Michelangelo Grosso, F. Melchiori, D. Loparco, Davide Appello, Luigi Dilillo, Alessandro Paccagnella, Matteo Sonza Reorda. 29-34 [doi]
• Evaluating transient-fault effects on traditional C-element s implementationsRodrigo Possamai Bastos, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis. 35-40 [doi]
• Probabilistic methods for the impact of an SET in combinational logicSreenivas Gangadhar, Spyros Tragoudas. 41-46 [doi]
• Analysis of on-line self-testing policies for real-time embedded multiprocessors in DSM technologiesOlivier Héron, Julien Guilhemsang, Nicolas Ventroux, Alain Giulieri. 49-55 [doi]
• Distributed online software monitoring of manycore architecturesEtienne Faure, Mounir Benabdenbi, François Pêcheux. 56-61 [doi]
• SBST for on-line detection of hard faults in multiprocessor applications under energy constraintsAndreas Merentitis, D. Margaris, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos. 62-67 [doi]
• An analog VLSI multilayer perceptron and its application towards built-in self-test in analog circuitsDzmitry Maliuk, Haralampos-G. D. Stratigopoulos, Yiorgos Makris. 71-76 [doi]
• Built-in performance monitoring of mixed-signal/RF front ends using real-time parameter estimationShyam Kumar Devarakond, Shreyas Sen, Aritra Banerjee, Vishwanath Natarajan, Abhijit Chatterjee. 77-82 [doi]
• Wavelet analysis of measurements for on-line testing analog & mixed-signal circuitsMichael Dimopoulos, Alexios Spyronasios, Alkis A. Hatzopoulos. 83-87 [doi]
• A framework to support the design of COTS-based reliable space computers for on-board data handlingSalvatore Campagna, Massimo Violante. 91-96 [doi]
• Checkpointing virtual machines against transient errorsLong Wang, Zbigniew Kalbarczyk, Ravishankar K. Iyer, Arun Iyengar. 97-102 [doi]
• Qualification and relifing testing for space applications applied to the agilent G-Link componentsMichel Pignol, Florence Malou, Corinne Aicardi. 103-108 [doi]
• Configurable serial fault-tolerant link for communication in 3D integrated systemsVladimir Pasca, Lorena Anghel, Claudia Rusu, Mounir Benabdenbi. 115-120 [doi]
• RILM: Reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chipClaudia Rusu, Lorena Anghel, Dimiter Avresky. 121-126 [doi]
• An FPGA-based fail-soft system with adaptive reconfigurationRyoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue. 127-132 [doi]
• Thermal coupling in ICs: Applications to the test and characterization of analogue and RF circuitsJosep Altet, Diego Mateo, Eduardo Aldrete-Vidrio. 135 [doi]
• Radiation effects on programmable analog devices and mitigation techniquesTiago R. Balen, Marcelo Lubaszewski. 136 [doi]
• Concepts for fault tolerant sensor systemsA. Richardson. 137 [doi]
• Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memoriesSebastiàn A. Bota, Gabriel Torrens, Bartomeu Alorda, J. Verd, Jaume Segura. 141-146 [doi]
• Programmable restricted SEC codes to mask permanent faults in semiconductor memoriesSamuel Evain, Yannick Bonhomme, Valentin Gherman. 147-153 [doi]
• A bit level area aware cache-based architecture for memory repairsNicholas Axelos, Kiamal Z. Pekmestzi. 154-158 [doi]
• A software-based self-test methodology for in-system testing of processor cache tag arraysGeorge Theodorou, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos. 159-164 [doi]
• An on-line fault detection technique based on embedded debug featuresMichelangelo Grosso, Matteo Sonza Reorda, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena. 167-172 [doi]
• A partitioning approach to improve reconfigurable neuron-inspired online BISTAli Shahabi, S. Behdad Hosseini, Hasan Sohofi, Zainalabedin Navabi. 173-178 [doi]
• Selecting state variables for improved on-line testability through output response comparison of identical circuitsIrith Pomeranz, Sudhakar M. Reddy. 179-184 [doi]
• A method for detecting resistive opens in busesJosep Rius. 187-189 [doi]
• A new framework for the automatic insertion of mitigation structures in circuits netlistsNiccolò Battezzati, Davide Serrone, Massimo Violante. 190-191 [doi]
• Application dependent FPGA testing method using compressed deterministic test vectorsMartin Rozkovec, Jiri Jenícek, Ondrej Novák. 192-193 [doi]
• Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty componentsZhen Zhang, Alain Greiner, Mounir Benabdenbi. 194-196 [doi]
• Improving fault handling software techniquesPiotr Gawkowski, Tomasz Rutkowski, Janusz Sosnowski. 197-199 [doi]
• Investigating the Use of BICS to detect resistive-open defects in SRAMsR. Chipana, Leticia Maria Veiras Bolzani, Fabian Vargas, Jorge Semião, Juan J. Rodríguez-Andina, Isabel C. Teixeira, Paulo J. Teixeira. 200-201 [doi]
• Online fault testing of reversible logic using dual rail codingNavid Farazmand, Masoud Zamani, Mehdi Baradaran Tahoori. 204-205 [doi]
• Reconfigurable low-power Concurrent Error Detection in logic circuitsSobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu. 206-207 [doi]
• Robust cryptographic ciphers with on-line statistical properties validationAnna Vaskova, Celia López-Ongil, Alejandro Jiménez-Horas, Enrique San Millán, Luis Entrena. 208-210 [doi]
• Trustworthy computing in a multi-core system using distributed schedulingDavid R. McIntyre, Francis G. Wolff, Christos A. Papachristou, Swarup Bhunia. 211-213 [doi]
• 3D integration: Circuit design, test, and reliability challengesNikolaos Minas, Ingrid De Wolf, Erik Jan Marinissen, Michele Stucchi, Herman Oprins, Abdelkarim Mercha, Geert Van der Plas, Dimitrios Velenis, Pol Marchal. 217 [doi]
• Interconnect Built-In Self-Repair and Adaptive-Serialization (I-BIRAS) for 3D integrated systemsMichael Nicolaidis, Vladimir Pasca, Lorena Anghel. 218 [doi]
• Test and reliability concerns for 3D-ICsYervant Zorian. 219 [doi]
• Evaluation of concurrent error detection techniques on the advanced encryption standardK. Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. 223-228 [doi]
• Key randomization using a power analysis resistant deterministic random bit generatorPaul Duplys, Eberhard Böhl, Wolfgang Rosenstiel. 229-234 [doi]
• How to flip a bit?Michel Agoyan, Jean-Max Dutertre, Amir-Pasha Mirbaha, David Naccache, Anne-Lise Ribotta, Assia Tria. 235-239 [doi]
• Robust FSMs for cryptographic devices resilient to strong fault injection attacksZhen Wang, Mark G. Karpovsky. 240-245 [doi]
• On-line detection of random voltage perturbations in buses with multiple-threshold receiversMichael N. Skoufis, Spyros Tragoudas. 249-254 [doi]
• Design of embedded constant weight code checkers based on averaging operationsSteffen Tarnick. 255-260 [doi]
• On-line testing of bundled-data asynchronous handshake protocolsSteffen Zeidler, Alexandre V. Bystrov, Milos Krstic, Rolf Kraemer. 261-267 [doi]
• Reducing the area overhead of TMR-systems by protecting specific signalsMichael Augustin, Michael Gössel, Rolf Kraemer. 268-273 [doi]
• Robust detection of soft errors using delayed capture methodologyV. Prasanth, Virendra Singh, Rubin A. Parekhji. 277-282 [doi]
• Timing error tolerance in nanometer ICsS. Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni. 283-288 [doi]
• Error resilient video encoding using Block-Frame ChecksumsJoshua W. Wells, Jayaram Natarajan, Abhijit Chatterjee. 289-294 [doi]