Nobuki Kajihara - researchr alias

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Viewing Publication 1 - 15 from 15

2024

FPGA Implementation for Large Scale Reservoir Computing based on Chaotic Boltzmann MachineShigeki Matsumoto, Yuki Ichikawa, Nobuki Kajihara, Hakaru Tamukoh. iscas 2024: 1-5 [doi]

2001

Implementation of a Gate-Level Evolvable Hardware ChipMasaya Iwata, Isamu Kajitani, Yong Liu, Nobuki Kajihara, Tetsuya Higuchi. ices 2001: 38-49 [doi]

Arithmetic Operation Oriented Reconfigurable Chip: RHWTsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara. fpl 2001: 618-622 [doi]

2000

Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHWTsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara. fccm 2000: 281-282 [doi]

1999

Evolvable Hardware Chips for Industrial ApplicationsTetsuya Higuchi, Nobuki Kajihara. CACM, 42(4):60-66, 1999. [doi]

Real-world applications of analog and digital evolvable hardware Tetsuya Higuchi, Masaya Iwata, Didier Keymeulen, Hidenori Sakanashi, Masahiro Murakawa, Isamu Kajitani, Eiichi Takahashi, Kenji Toda, Mehrdad Salami, Nobuki Kajihara, Nobuyuki Otsu. tec, 3(3):220-235, 1999.

An Evolvable Hardware Chip and Its Application as a Multi-Function Prosthetic Hand ControllerIsamu Kajitani, Tsutomu Hoshino, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi. AAAI 1999: 182-187

Evolvable Hardware Chips for Neural Network ApplicationsIsamu Kajitani, Masahiro Murakawa, Nobuki Kajihara, Masaya Iwata, Hidenori Sakanashi, Tetsuya Higuchi. icannga 1999: 127-134 [doi]

The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network ProcessingMasahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Xin Yao, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi. TC, 48(6):628-639, 1999.

1998

1996

SOP: a reconfigurable massively parallel system and its control-data-flow based compiling methodTsukasa Yamauchi, Shogo Nakaya, Nobuki Kajihara. fccm 1996: 148-156 [doi]

SOP: An Adaptive Massively Parallel Computer and its Control-Data-Flow Based Compiling MethodTsukasa Yamauchi, Shogo Nakaya, Nobuki Kajihara. parcella 1996: 128-136

1989

MAN-YO: Mixed level parallel logic simulation engineNobuhiko Koike, Toshiyuki Nakata, Nobuki Kajihara. scjapan, 20(10):31-38, 1989. [doi]

1988

Parallel neural network simulation machine: NeumanNobuki Kajihara, Satoshi Matsushita, Toshiyuki Nakata, Nobuhiko Koike. NN, 1(Supplement-1):544, 1988. [doi]

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