Abstract is missing.
- A high-level EDA environment for the automatic insertion of HD-BIST structuresAlfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian. 2-6 [doi]
- On calculating efficient LFSR seeds for built-in self testChristophe Fagot, Olivier Gascuel, Patrick Girard 0001, Christian Landrault. 7-14 [doi]
- On random pattern testability of cryptographic VLSI coresA. Schubert, Walter Anheier. 15-20 [doi]
- Functional and structural testing of switched-current circuitsMichel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand. 22-27 [doi]
- Practical implementation of defect-oriented testing for a mixed-signal class-D amplifierR. H. Beurze, Y. Xing, R. van Kleef, Ronald J. W. T. Tangelder, Nur Engin. 28-33 [doi]
- A new approach for the nonlinearity test of ADCs/DACs and its application for BISTFang Xu. 34-38 [doi]
- Compaction of IDDQ test sequence using reassignment methodToshiyuki Maeda, Kozo Kinoshita. 40-45 [doi]
- Experimental results on BIC sensors for transient current testingRodrigo Picos, Miquel Roca, Eugeni Isern, J. Segura, Enrique García-Moreno. 46-50 [doi]
- Application of supply current testing to analogue circuits, towards a structural analogue test methodologyHans A. R. Manhaeve, Johan Verfaillie, B. Straka, J. P. Cornil. 51-56 [doi]
- A DFT for semi-DC fault diagnosis for switched-capacitor circuitsSheng-Jer Kuo, Chung-Len Lee, Soon-Jyh Chang, Jwu E. Chen. 58-63 [doi]
- Extending fault-based testing to microelectromechanical systemsSalvador Mir, Benoît Charlot, Bernard Courtois. 64-68 [doi]
- The role of test protocols in testing embedded-core-based system ICsErik Jan Marinissen, Maurice Lousberg. 70-75 [doi]
- Debug facilities in the TriMedia CPU64 architectureHarald Vranken. 76-81 [doi]
- High-level path activation technique to speed up sequential circuit test generationJaan Raik, Raimund Ubar. 84-89 [doi]
- On avoiding undetectable faults during test generationIrith Pomeranz, Sudhakar M. Reddy. 90-95 [doi]
- A scalable BIST architecture for delay faultsMartin Keim, Ilia Polian, Harry Hengster, Bernd Becker 0001. 98-103 [doi]
- Partial set for flip-flops based on state requirement for non-scan BIST schemeMarie-Lise Flottes, Christian Landrault, A. Petitqueux. 104-109 [doi]
- Deterministic BIST with partial scanGundolf Kiefer, Hans-Joachim Wunderlich. 110-116 [doi]
- On the fault-injection-caused increase of the DAE-index in analogue fault simulationBernd Straube, Kurt Reinschke, Wolfgang Vermeiren, Klaus Röbenack, Bert Müller, Christoph Clauß. 118-122 [doi]
- On maximizing the coverage of catastrophic and parametric faultsAnna Maria Brosa, Joan Figueras. 123-128 [doi]
- Using the BS register for capturing and storing n-bit sequences in real-timeGustavo Ribeiro Alves, José Manuel Martins Ferreira. 130-135 [doi]
- From system level to defect-oriented test: a case studyOctávio Páscoa Dias, Jorge Semião, Marcelino B. Santos, Isabel Maria Cacho Teixeira, João Paulo Teixeira. 136-141 [doi]
- Cost effective testing of systems on silicon: areas for optimizationPeter Muhmenthaler. 142-143 [doi]
- Test configuration minimization for the logic cells of SRAM-based FPGAs: a case studyMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian. 146-151 [doi]
- Design of an automatic testing for FPGAsAbderrahim Doumar, Toshiaki Ohmameuda, Hideo Ito. 152-157 [doi]
- A new BIST architecture for low power circuitsFulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante. 160-164 [doi]
- Low power BIST by filtering non-detecting vectorsSalvador Manich, A. Gabarró, M. Lopez, Joan Figueras, P. Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, P. Teixeira, Marcelino B. Santos. 165-170 [doi]