Table of Contents

• On the Road to a Mobile Information SocietyDirk Friebel. 3 [doi]
• Architectural Impact of Secure Socket Layer on Internet ServersKrishna Kant, Ravishankar K. Iyer, Prasant Mohapatra. 7-14 [doi]
• Sleipnir - An Instruction-Level Simulator GeneratorTor E. Jeremiassen. 23 [doi]
• Analog Transient Concurrent Fault Simulation with Dynamic Fault GroupingJunwei Hou, Abhijit Chatterjee. 35-41 [doi]
• Pseudoexhaustive TPG with a Provably Low Number of LFSR SeedsDimitrios Kagaris, Spyros Tragoudas. 42-47 [doi]
• An Application of Genetic Algorithms and BDDs to Functional TestingFabrizio Ferrandi, Donatella Sciuto, Alessandro Fin, Franco Fummi. 48 [doi]
• High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) TechnologyChulwoo Kim, Jaesik Lee, Kwang-Hyun Baek, Eric Martina, Sung-Mo Kang. 59-64 [doi]
• Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS CircuitsShiyou Zhao, Kaushik Roy, Cheng-Kok Koh. 65-72 [doi]
• Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous SystemsSimon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson. 73 [doi]
• Hybridizing and Coalescing Load Value PredictorsMartin Burtscher, Benjamin G. Zorn. 81-92 [doi]
• A 2-Way Thrashing-Avoidance Cache (TAC): An Efficient Instruction Cache Scheme for Object-Oriented LanguagesYul Chu, Mabo Robert Ito. 93-98 [doi]
• Architectural Support for Dynamic Memory ManagementJ. Morris Chang, Witawas Srisa-an, Chia-Tien Dan Lo. 99-104 [doi]
• SCIMA: Software Controlled Integrated Memory Architecture for High Performance ComputingMasaaki Kondo, Hideki Okawara, Hiroshi Nakamura, Taisuke Boku. 105 [doi]
• Worst Delay Estimation in Crosstalk Aware Static Timing AnalysisTong Xiao, Malgorzata Marek-Sadowska. 115-120 [doi]
• Analysis and Optimization of Ground Bounce in Digital CMOS CircuitsPayam Heydari, Massoud Pedram. 121-126 [doi]
• An Efficient and Accurate Model for RF/Microwave Spiral Inductors Using Microstrip Lines TheoryNasser Masoumi, Safieddin Safavi-Naeini, Mohamed I. Elmasry. 127-132 [doi]
• Comparative Study of Parallel Algorithms for 3-D Capacitance Extraction on Distributed Memory MultiprocessorsYanhong Yuan, Prithviraj Banerjee. 133 [doi]
• A Novel Low-Power Microprocessor ArchitectureRolf Hakenes, Yiannos Manoli. 141-146 [doi]
• A Power Perspective of Value Speculation for Superscalar MicroprocessorsRafael A. Moreno, Luis Piñuel, Silvia Del Pino, Francisco Tirado. 147-154 [doi]
• Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar ArchitecturesDeependra Talla, Lizy Kurian John, Viktor S. Lapinskii, Brian L. Evans. 163 [doi]
• Unified Fine-Granularity Buffering of Index and Data: Approach and ImplementationQiang Cao, Josep Torrellas, H. V. Jagadish. 175-186 [doi]
• Analysis of Shared Memory Misses and Reference PatternsJeffrey B. Rothman, Alan Jay Smith. 187-198 [doi]
• Power-Sensitive Multithreaded ArchitectureJohn S. Seng, Dean M. Tullsen, George Cai. 199 [doi]
• Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate SizingI-Min Liu, Adnan Aziz. 209-214 [doi]
• Application-Based, Transistor-Level Full-Chip Power Analysis for 700 MHz PowerPC:::TM::: MicroprocessorYi-Kan Cheng, David Bearden, Kanti Suryadevara. 215-220 [doi]
• Buffer Library SelectionJosé Luis Neves, Stephen T. Quay. 221-226 [doi]
• Current-Mode Threshold Logic GatesSudhakar Bobba, Ibrahim N. Hajj. 235-240 [doi]
• Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit FamilyAlexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar. 241-246 [doi]
• Output Prediction Logic: A High-Performance CMOS Design TechniqueLarry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Carl Sechen. 247 [doi]
• The Future of Populist ParallelismGregory F. Pfister. 257 [doi]
• A Study of Channeled DRAM Memory ArchitecturesLars Friebe, Yoshikazu Yabe, Masato Motomura. 261-266 [doi]
• DRAM-Page Based Prediction and PrefetchingHaifeng Yu, Gershon Kedem. 267-275 [doi]
• Reducing Cost and Tolerating Defects in Page-based Intelligent MemoryMark Oskin, Diana Keen, Justin Hensley, Lucian Vlad Lita, Frederic T. Chong. 276 [doi]
• A Selective Temporal and Aggressive Spatial Cache System Based on Time IntervalJung Hoon Lee, Jang-Soo Lee, Shin-Dug Kim. 287-293 [doi]
• A Trace Based Evaluation of Speculative Branch DecouplingAnshuman S. Nadkarni, Akhilesh Tyagi. 300 [doi]
• An Adder Using Charge Sharing and its Application in DRAMsHak-soo Yu, Songjun Lee, Jacob A. Abraham. 311-317 [doi]
• Dynamic Flip-Flop with Improved PowerNikola Nedovic, Vojin G. Oklobdzija. 323 [doi]
• AMULET3: A 100 MIPS Asynchronous Embedded ProcessorStephen B. Furber, David A. Edwards, Jim D. Garside. 329-334 [doi]
• Xtensa with User Defined DSP Coprocessor MicroarchitecturesGülbin Ezer. 335-342 [doi]
• Predictive Strategies for Low-Power RTOS SchedulingPavan Kumar, Mani B. Srivastava. 343 [doi]
• Rectilinear Block Placement Using B*-TreesGuang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang. 351-356 [doi]
• Fast Hierarchical Floorplanning with Congestion and Timing ControlAbhishek Ranjan, Kia Bazargan, Majid Sarrafzadeh. 357-362 [doi]
• An Evaluation of Move-Based Multi-Way Partitioning AlgorithmsElie Yarack, Joan Carletta. 363-369 [doi]
• Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan SynthesisKoji Ohashi, Mineo Kaneko, Satoshi Tayu. 370 [doi]
• On Solving Stack-Based Incremental Satisfiability ProblemsJoonyoung Kim, Jesse Whittemore, Karem A. Sakallah. 379-382 [doi]
• Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound ComputationWolfgang Günther, Rolf Drechsler, Stefan Höreth. 383-388 [doi]
• Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test GenerationIrith Pomeranz, Sudhakar M. Reddy. 389-394 [doi]
• On Test Application Time and Defect Detection Capabilities of Test Sets for Scan DesignsIrith Pomeranz, Sudhakar M. Reddy. 395 [doi]
• Effective Hardware-Based Two-Way Loop Cache for High Performance Low Power ProcessorsTim Anderson, Sanjive Agarwala. 403-407 [doi]
• A Multi-Level Memory System Architecture for High-Performance DSP ApplicationsSanjive Agarwala, Charles Fuoco, Tim Anderson, Dave Comisky, Christopher Mobley. 408-413 [doi]
• A Scalable High-Performance DMA Architecture for DSP ApplicationsDave Comisky, Sanjive Agarwala, Charles Fuoco. 414 [doi]
• PEAS-III: An ASIP Design EnvironmentMakiko Itoh, Shigeaki Higaki, Yoshinori Takeuchi, Akira Kitajima, Masaharu Imai, Jun Sato, Akichika Shiomi. 430-436 [doi]
• Symbolic Binding for Clustered VLIW ASIPsSatish Pillai, Margarida F. Jacome. 437-444 [doi]
• Interfacing Hardware and Software Using C++ Class LibrariesDinesh Ramanathan, Rajesh K. Gupta, Raymond Roth. 445 [doi]
• Formal Verification of an Industrial System-on-a-ChipHoon Choi, Myung-Kyoon Yim, Jae Young Lee, Byeong-Whee Yun, Yun-Tae Lee. 453-458 [doi]
• An Automatic Validation Methodology for Logic BIST in High Performance VLSI DesignMichael Cogswell, Don Pearl, James Sage, Alan Troidl. 473 [doi]
• The Birth of the BabyHilary J. Kahn, R. B. E. Napper. 481 [doi]
• Efficient Logic Optimization Using Regularity ExtractionThomas Kutzschebauch. 487-493 [doi]
• Binary and Multi-Valued SPFD-Based Wire Removal in PLA NetworksSubarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 494-503 [doi]
• Minimization of Ordered Pseudo Kronecker Decision DiagramsPer Lindgren, Rolf Drechsler, Bernd Becker. 504 [doi]
• Rethinking Behavioral Synthesis for a Better Integration within Existing Design FlowsWander O. Cesário, Ahmed Amine Jerraya, Zoltan Sugar, Imed Moussa. 513-518 [doi]
• Multi-Level Communication Synthesis of Heterogeneous Multilanguage SpecificationF. Hessel, Philippe Coste, Gabriela Nicolescu, P. LeMarrec, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya. 525 [doi]
• Low Power Video Object Motion-Tracking Architecture for Very Low Bit Rate Online Video ApplicationsWael M. Badawy, Magdy A. Bayoumi. 533-536 [doi]
• An SEU Injection Tool to Evaluate DSP-Based Architectures for Space ApplicationsAlfredo Benso, Stefano Martinetto, Paolo Prinetto, Riccardo Mariani. 537-538 [doi]
• On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCsAlfredo Benso, Stefano Di Carlo, Silvia Chiusano, Paolo Prinetto, Fabio Ricciato, Monica Lobetti Bodoni, Maurizio Spadari. 539-540 [doi]
• Static Timing Analysis with False PathsHaizhou Chen, Bing Lu, Ding-Zhu Du. 541-544 [doi]
• A Methodology and Tool for Automated Transformational High-Level Design Space ExplorationJoachim Gerlach, Wolfgang Rosenstiel. 545-548 [doi]
• Cheap Out-of-Order Execution Using Delayed IssueJ. P. Grossman. 549-551 [doi]
• Representing and Scheduling Looping Behavior SymbolicallySteve Haynal, Forrest Brewer. 552-555 [doi]
• A Register File with Transposed Access ModeYoochang Jung, Stefan G. Berg, Donglok Kim, Yongmin Kim. 559-560 [doi]
• Leakage Power Analysis and Reduction during Behavioral SynthesisKamal S. Khouri, Niraj K. Jha. 561-564 [doi]
• An Advanced Instruction Folding Mechanism for a Stackless Java ProcessorAustin Kim, J. Morris Chang. 565-566 [doi]
• OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the InternetHemang Lavana, Franc Brglez, Robert B. Reese, Gangadhar Konduri, Anantha Chandrakasan. 567-570 [doi]
• A Decompression Architecture for Low Power Embedded SystemsHaris Lekatsas, Jörg Henkel, Wayne Wolf. 571-574 [doi]
• Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable ArchitecturesRafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh. 575-576 [doi]
• The M·CORE:::TM::: M340 Unified Cache ArchitectureAfzal Malik, Bill Moyer, Dan Cermak. 577-580 [doi]
• Crosstalk-Constrained Performance Optimization by Using Wire Sizing and PerturbationSong-Ra Pan, Yao-Wen Chang. 581-584 [doi]
• Hierarchical Simulation of a Multiprocessor ArchitectureMarius Pirvu, Laxmi N. Bhuyan, Rabi N. Mahapatra. 585-588 [doi]
• On Multiple Precision Based Montgomery Multiplication without Precomputation of N0´ = -N0-1 mod WHagen Ploog, Dirk Timmermann. 589-590 [doi]
• A Technique for Identifying RTL and Gate-Level CorrespondencesSrivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana. 591 [doi]
• A Direct Mapping FPGA Architecture for Industrial Process Control ApplicationsJohn T. Welch, Joan Carletta. 595-598 [doi]
• Source-Level Transformations for Improved Formal VerificationBrian D. Winters, Alan J. Hu. 599 [doi]
• Processors for Mobile ApplicationsFarinaz Koushanfar, Miodrag Potkonjak, Vandana Prabhu, Jan M. Rabaey. 603-608 [doi]