Robert D. Mullins - researchr alias

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Viewing Publication 1 - 31 from 31

2024

ImpNet: Imperceptible and blackbox-undetectable backdoors in compiled neural networksEleanor Clifford, Ilia Shumailov, Yiren Zhao, Ross J. Anderson, Robert D. Mullins. satml 2024: 344-357 [doi]

2023

2022

2021

Lane Compression: A Lightweight Lossless Compression Method for Machine Learning on Embedded SystemsYousun Ko, Alex Chadwick, Daniel Bates, Robert D. Mullins. tecs, 20(2), 2021. [doi]

Sponge Examples: Energy-Latency Attacks on Neural NetworksIlia Shumailov, Yiren Zhao, Daniel Bates, Nicolas Papernot, Robert D. Mullins, Ross Anderson 0001. eurosp 2021: 212-231 [doi]

2020

2019

Efficient Winograd or Cook-Toom Convolution Kernel Implementation on Widely Used Mobile CPUsPartha Maji, Andrew Mundy, Ganesh Dasika, Jesse G. Beu, Matthew Mattina, Robert D. Mullins. emc2 2019: 1-5 [doi]

To Compress Or Not To Compress: Understanding The Interactions Between Adversarial Attacks And Neural Network CompressionYiren Zhao, Ilia Shumailov, Robert D. Mullins, Ross Anderson 0001. mlsys 2019: [doi]

2018

2013

Designing a Physical Locality Aware Coherence Protocol for Chip-MultiprocessorsChristian Fensch, Nick Barrow-Williams, Robert D. Mullins, Simon W. Moore. TC, 62(5):914-928, 2013. [doi]

2009

An Energy and Performance Exploration of Network-on-Chip ArchitecturesArnab Banerjee, Pascal T. Wolkotte, Robert D. Mullins, Simon W. Moore, Gerard J. M. Smit. tvlsi, 17(3):319-329, 2009. [doi]

2008

A Network of Time-Division Multiplexed Wiring for FPGAsRosemary M. Francis, Simon W. Moore, Robert D. Mullins. nocs 2008: 35-44 [doi]

2007

A Power and Energy Exploration of Network-on-Chip ArchitecturesArnab Banerjee, Robert D. Mullins, Simon W. Moore. nocs 2007: 163-172 [doi]

Demystifying Data-Driven and Pausible Clocking SchemesRobert D. Mullins, Simon W. Moore. async 2007: 175-185 [doi]

2006

The design and implementation of a low-latency on-chip networkRobert D. Mullins, Andrew West, Simon W. Moore. aspdac 2006: 164-169 [doi]

2004

Low-Latency Virtual-Channel Routers for On-Chip NetworksRobert D. Mullins, Andrew West, Simon W. Moore. isca 2004: 188-197 [doi]

2003

Security Evaluation of Asynchronous CircuitsJacques J. A. Fournier, Simon W. Moore, Huiyun Li, Robert D. Mullins, George S. Taylor. ches 2003: 137-151 [doi]

Balanced self-checking asynchronous logic for smart card applicationsSimon W. Moore, Ross J. Anderson, Robert D. Mullins, George S. Taylor, Jacques J. A. Fournier. mam, 27(9):421-430, 2003. [doi]

2002

Improving Smart Card Security Using Self-Timed CircuitsSimon W. Moore, Robert D. Mullins, Paul A. Cunningham, Ross J. Anderson, George S. Taylor. async 2002: 211 [doi]

Point to Point GALS InterconnectGeorge S. Taylor, Simon W. Moore, Robert D. Mullins, Peter Robinson. async 2002: 69-75 [doi]

2000

Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous SystemsSimon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson. iccd 2000: 73 [doi]

1999

A Fully Asynchronous Superscalar ArchitectureD. K. Arvind, Robert D. Mullins. IEEEpact 1999: 17-22 [doi]

1995

Micronets: a model for decentralising control in asynchronous processor architecturesD. K. Arvind, Robert D. Mullins, Vinod E. F. Rebello. async 1995: 190-199 [doi]

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