Abstract is missing.
- One look into the future of CMOS chip designCarl J. Anderson. 1-2 [doi]
- Early analysis for power distribution networksKai Wang, Aveek Sarkar, Norman Chang, Shen Lin. 3-4 [doi]
- Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designsWan-Ping Lee, Diana Marculescu, Yao-Wen Chang. 5-12 [doi]
- Multi-voltage floorplan design with optimal voltage assignmentQian Zaichen, Evangeline F. Y. Young. 13-18 [doi]
- Robust interconnect communication capacity algorithm by geometric programmingJifeng Chen, Jin Sun, Janet Meiling Wang. 19-26 [doi]
- A new algorithm for simultaneous gate sizing and threshold voltage assignmentYifang Liu, Jiang Hu. 27-34 [doi]
- On stress aware active area sizing, gate sizing, and repeater insertionAshutosh Chakraborty, David Z. Pan. 35-42 [doi]
- Fast buffering for optimizing worst slack and resource consumption in repeater treesChristoph Bartoschek, Stephan Held, Dieter Rautenbach, Jens Vygen. 43-50 [doi]
- On improving optimization effectiveness in interconnect-driven physical synthesisPrashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer. 51-58 [doi]
- Will 22nm be our catch 22!: design and cad challengesRuchir Puri. 59-60 [doi]
- Vertical slit transistor based integrated circuits (VeSTICs) paradigmWojciech Maly. 63-64 [doi]
- Graphene based transistors: physics, status and future perspectivesKaustav Banerjee, Yasin Khatami, Chaitanya Kshirsagar, Seid Hadi Rasouli. 65-66 [doi]
- Accelerated design of analog, mixed-signal circuits in TitanAnirudh Devgan, Bulent Basaran, David Colleran, Mar Hershenson. 67-72 [doi]
- Physical design methodology for analog circuitsin a system-on-a-chip environmentEric Soenen. 73-74 [doi]
- Constraint-driven design: the next step towards analog design automationGöran Jerke, Jens Lienig. 75-82 [doi]
- Transistor-level layout of high-density regular circuitsYi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly. 83-90 [doi]
- Physical optimization for FPGAs using post-placement topology rewritingVal Pevzner, Andrew A. Kennings, Andy Fox. 91-98 [doi]
- A routing approach to reduce glitches in low power FPGAsQuang Dinh, Deming Chen, Martin D. F. Wong. 99-106 [doi]
- Double patterning layout decomposition for simultaneous conflict and stitch minimizationKun Yuan, Jae-Seok Yang, David Z. Pan. 107-114 [doi]
- An automatic optical-simulation-based lithography hotspot fix flow for post-route optimizationYang-Shan Tong, Chia-Wei Lin, Sao-Jie Chen. 115-122 [doi]
- Redundant via insertion with wire bendingKuang-Yao Lee, Shing-Tung Lin, Ting-Chi Wang. 123-130 [doi]
- Wire shaping is practicalHongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng. 131-138 [doi]
- Industrial clock designPei-Hsin Ho. 139-140 [doi]
- An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessorsRupesh S. Shelar. 141-148 [doi]
- Ispd2009 clock network synthesis contestCliff N. Sze, Phillip Restle, Gi-Joon Nam, Charles J. Alpert. 149-150 [doi]
- Critical-trunk based obstacle-avoiding rectilinear steiner tree routings for delay and slack optimizationYen-Hung Lin, Shu-Hsin Chang, Yih-Lang Li. 151-158 [doi]
- Robust layer assignment for via optimization in multi-layer global routingTsung-Hsien Lee, Ting-Chi Wang. 159-166 [doi]
- A faster approximation scheme for timing driven minimum cost layer assignmentShiyan Hu, Zhuo Li, Charles J. Alpert. 167-174 [doi]
- Diffusion-driven congestion reduction for substrate topological routingShenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong. 175-180 [doi]
- The challenges of correlating silicon and models in high variability CMOS processesRobert C. Aitken. 181-182 [doi]
- Synthesizing a representative critical path for post-silicon delay predictionQunzeng Liu, Sachin S. Sapatnekar. 183-190 [doi]
- A metal-only-ECO solver for input-slew and output-loading violationsChien Pang Lu, Mango Chia-Tso Chao, Chen Hsing Lo, Chih-Wei Chang. 191-198 [doi]