Abstract is missing.
- Invited Talk 2 - Optical Interconnects for Backplane and Chip-to-Chip PhotonicsIan H. White, Richard V. Penty. [doi]
- Invited Talk 1- Past, Present, and Future Communicating ProcessorsDavid May. [doi]
- Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on ChipBart Vermeulen, Kees Goossens, Siddharth Umrani. 3-12 [doi]
- A Lightweight Fault-Tolerant Mechanism for Network-on-ChipMichihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston. 13-22 [doi]
- Adding Slow-Silent Virtual Channels for Low-Power On-Chip NetworksHiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano. 23-32 [doi]
- A Network of Time-Division Multiplexed Wiring for FPGAsRosemary M. Francis, Simon W. Moore, Robert D. Mullins. 35-44 [doi]
- Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration InterconnectsKees Goossens, Martijn T. Bennebroek, Jae Young Hur, Muhammad Aqeel Wahlah. 45-54 [doi]
- ReNoC: A Network-on-Chip Architecture with Reconfigurable TopologyMikkel Bystrup Stensgaard, Jens Sparsø. 55-64 [doi]
- SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip NetworksAlireza Ejlali, Bashir M. Al-Hashimi. 67-76 [doi]
- Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-ChipPo-Tsang Huang, Wei-Li Fang, Yin-Ling Wang, Wei Hwang. 77-83 [doi]
- An Efficient Implementation of Distributed Routing Algorithms for NoCsJose Flich, Samuel Rodrigo, José Duato. 87-96 [doi]
- Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip PlatformsMaurizio Palesi, Giuseppe Longo, Salvatore Signorino, Rickard Holsmark, Shashi Kumar, Vincenzo Catania. 97-106 [doi]
- Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis FrameworkFrancisco Gilabert Villamón, Simone Medardoni, Davide Bertozzi, Luca Benini, María Engracia Gómez, Pedro López, José Duato. 107-116 [doi]
- Impact of Process and Temperature Variations on Network-on-Chip Design ExplorationBin Li, Li-Shiuan Peh, Priyadarsan Patra. 117-126 [doi]
- Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoCEdith Beigné, Fabien Clermidy, Sylvain Miermont, Pascal Vivet. 129-138 [doi]
- Physical Implementation of the DSPIN Network-on-Chip in the FAUST ArchitectureIvan Miro Panades, Fabien Clermidy, Pascal Vivet, Alain Greiner. 139-148 [doi]
- A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and ApplicationXuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach. 149-158 [doi]
- Real-Time Communication Analysis for On-Chip Networks with Wormhole SwitchingZheng Shi, Alan Burns. 161-170 [doi]
- Statistical Approach to NoC DesignItamar Cohen, Ori Rottenstreich, Isaac Keslassy. 171-180 [doi]
- Reducing the Interconnection Network Cost of Chip MultiprocessorsPablo Abad, Valentin Puente, José-Ángel Gregorio. 183-192 [doi]
- Circuit-Switched CoherenceNatalie D. Enright Jerger, Li-Shiuan Peh, Mikko H. Lipasti. 193-202 [doi]
- Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive NetworkSuboh A. Suboh, Mohamed Bakhouya, Tarek A. El-Ghazawi. 205-206 [doi]
- Low-Cost VC Allocator Design for Virtual Channel Wormhole Routers in Networks-on-ChipMin Zhang, Chiu-sing Choy. 207-208 [doi]
- Network Simplicity for Latency Insensitive CoresDaniel Gebhardt, JunBok You, W. Scott Lee, Kenneth S. Stevens. 209-210 [doi]
- Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on ChipAndreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, Marco Bekooij. 211-212 [doi]
- Implementation of Wave-Pipelined Interconnects in FPGAsTerrence S. T. Mak, Crescenzo D Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk. 213-214 [doi]
- An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net SimulatorLuis A. Plana, John Bainbridge, Steve Furber, Sean Salisbury, Yebin Shi, Jian Wu. 215-216 [doi]
- Dual-Channel Access Mechanism for Cost-Effective NoC DesignShijun Lin, Li Su, Depeng Jin, Lieguang Zeng. 217-218 [doi]