Rapidus Corporation US

Earlier today at a ceremony in Hokkaido, we announced the delivery of ASML’s EUV lithography equipment that will be installed in our advanced foundry, IIM-1. This is a significant milestone for Japan’s semiconductor industry, marking the first time that an EUV lithography tool will be used for mass production in the country. We’re very proud of our latest foundry milestone and as we look ahead to 2025, we’re excited for all that is to come in the new year. Read more here: https://lnkd.in/g6qb5YG2

In another important #EDA milestone, Rapidus is collaborating with Cadence to provide co-optimized #AI-driven reference design flows and a broad IP portfolio. The new collaboration will support the Rapidus 2nm gate-all-around process and leverage the design and manufacturing benefits from its backside power delivery network technology to provide design solutions and IP portfolio to customers. Check out the news here: https://lnkd.in/gRtUDgwA #SEMICONJapan

#SEMICONJapan is kicking off today and we’re looking forward to a great show. Come see us in booth #2148 to chat about the #EDA news we’re announcing.   Rapidus has signed an agreement with Synopsys Inc to enable a solution that will shorten semiconductor design cycle time, using a revolutionary new approach to natively model process sensitivity and variation in the design steps. This new approach dramatically reduces the need for expensive re-characterization of libraries and memories during different phases of the process evolution leading to a significant reduction in design iterations and acceleration of the overall project execution cycle. Read more here: https://lnkd.in/gK4TEvcS

Today at the annual IEEE International Electron Devices Meeting (IEDM) in San Francisco, we shared details on a significant milestone achieved with IBM Research. We unveiled a new chip construction process, called selective layer reductions, that is helping overcome some of the critical challenges to produce 2nm transistors and beyond at scale within the decade.   Scientists from IBM and Rapidus reached a critical breakthrough in consistently constructing chips with a 2nm process. Using two different strategies for selective nanosheet layer reduction, they can now build nanosheet gate-all-around transistors with multiple threshold voltages (or multi-Vt), which allows for chips that can perform complex computations without requiring as much energy. The group found that they could do this without the metal gate boundary problems that tend to accompany this construction method. Check out the findings on the IBM Research blog: https://lnkd.in/gg5jJiKD

With #SC24 taking place this week, the industry is buzzing with excitement around the release of the bi-annual listing of the #Top500 supercomputing systems. Congratulations to El Capitan from the Lawrence Livermore National Laboratory which reached a record performance of 1.742 exaflops. Read more here: https://lnkd.in/guqVM87j

There’s a new installation at New Chitose Airport (CTS) in Hokkaido, Japan! In the Domestic Terminal 3F, check out our display where you can see our new IIM facility currently under construction.

Exciting semiconductor news from the U.S.! The U.S. Department of Commerce announced that NY CREATES' Albany NanoTech Complex will house the NSTC EUV Accelerator, a key facility that will help secure leading-edge semiconductor research, development and manufacturing in North America. Congratulations to all! https://lnkd.in/eHGmTvch

#TBT – last month Henri Richard was featured on Electronic Design's #InsideElectronics podcast discussing the latest in logic-chip fabrication and Rapidus’ unique approach to semiconductor manufacturing. Check it out! https://lnkd.in/gFAAvjfV

We’re very excited to have Stephen DiFranco join Rapidus Design Solutions as head of marketing and partnerships. Stephen will lead and grow our partner ecosystem and external marketing efforts, while also supporting sales and customer advancements as we bring to market advanced 2nm semiconductors. Welcome, Stephen! https://lnkd.in/gwGKxKNM

At a groundbreaking ceremony yesterday, we announced that Rapidus will set up a clean room within Seiko Epson Corporation's facility in Chitose, Hokkaido, and open a research-and-development center for semiconductor packaging called Rapidus Chiplet Solutions (RCS). We were pleased to be joined by (📷 from left to right): - Yasunori Yoshino, Director, Executive Officer, and Chief Operating Officer, General Administrative Manager, Corporate Strategy Division, Seiko Epson - Yasunori Ogawa, President and Representative Director, Seiko Epson - Atsuyoshi Koike, CEO, Rapidus - Yasumitsu Orii, Senior Managing Executive Officer, Head of 3D Assembly Division, Rapidus   Read more: https://lnkd.in/g8A8jnnR